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ks8995ma/fq integrated 5-port 10/100 managed switch rev 2.9 micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? te l +1 (408) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.micre l.com september 2008 m9999-091508 general description the ks8995ma/fq is a highly integrated layer 2 managed switch with optimized bill of materials (bom) cost for low port count, cost-sensitive 10/100mbps switch systems with both copper and optic fiber media. it also provides an extens ive feature set such as tag/port-based vlan, quality of service (qos) priority, management, mib counters, dual mii interfaces and cpu control/data interfaces to effectively address both current and emerging fast ethernet applications. the ks8995ma/fq contains five 10/100 transceivers with patented mixed-signal low-power technology, five media access control (mac) units, a high-speed non- blocking switch fabric, a dedicated address lookup engine, and an on-chip frame buffer memory. all phy units support 10base-t and 100base-tx. in addition, two of the phy units support 100base-fx (ks8995ma is ports 4 and 5, ks8995fq is port 3 and port 4). functional diagram
micrel, inc. ks8995ma/fq semptember 2008 2 m9999-091508 1k look up engine queue mgmnt 10/100 mac 1 buffer mgmnt frame buffers fifo, flow control, vlan tagging, priority 10/100 mac 2 10/100 mac 3 10/100 mac 4 10/100 mac 5 sni 10/100 t/tx 1 10/100 t/tx 2 10/100 t/tx/fx 3 10/100 t/tx/fx 4 10/100 t/tx 5 spi eeprom i/f led i/f auto mdi/mdix control reg i/f mib counters mii- sw or sni led0[5:1] led1[5:1] led2[5:1] control registers mii-p5 mdc, mdi/o auto mdi/mdix auto mdi/mdix auto mdi/mdix auto mdi/mdix ksz8995fq notes: 1. ks8995ma has either tx copper or fx fiber for port 4 and port 5, other ports are the tx copper only. 2. ks8995fq has either tx copper or fx fiber for por t 3 and port 4, other ports are the tx copper only.
micrel, inc. ks8995ma/fq semptember 2008 3 m9999-091508 features ? integrated switch with five macs and five fast ethernet transceivers fully compliant to ieee 802.3u standard ? shared memory based switch fabric with fully non- blocking configuration ? 1.4gbps high-performance memory bandwidth ? 10base-t, 100base-tx, and 100base-fx modes ? dual mii configuration: mii-switch (mac or phy mode mii) and mii-p5 (phy mode mii) ? ieee 802.1q tag-based vlan (16 vlans, full-range vid) for dmz port, wan/lan separation or inter- vlan switch links ? vlan id tag/untag options, per-port basis ? programmable rate limiting 0mbps to 100mbps, ingress and egress port, rate options for high and low priority, per-port basis in 32kbps increments ? flow control or drop packet rate limiting (ingress port) ? integrated mib counters for fully compliant statistics gathering, 34 mib counters per port ? enable/disable option for huge frame size up to 1916 bytes per frame ? igmp v1/v2 snooping for multicast packet filtering ? special tagging mode to send cpu info on ingress packet?s port value ? spi slave (complete) and mdio (mii phy only) serial management interface for control of register configuration ? mac-id based security lock option ? control registers configurable on-the-fly (port-priority, 802.1p/d/q, an...) ? cpu read access to mac forwarding table entries ? 802.1d spanning tree protocol ? port mirroring/monitoring/sniffing: ingress and/or egress traffic to any port or mii ? broadcast storm protection with % control ? global and per-port basis ? optimization for fiber-to- copper media conversion ? full-chip hardware power-down support (register configuration not saved) ? per-port based software power-save on phy (idle link detection, register c onfiguration preserved) ? qos/cos packets prioritization supports: per port, 802.1p and diffserv based ? 802.1p/q tag insertion or removal on a per-port basis (egress) ? mdc and mdi/o interface support to access the mii phy control registers (not all control registers) ? mii local loopback support ? on-chip 64kbyte memory for frame buffering (not shared with 1k unicast address table) ? wire-speed reception and transmission ? integrated look-up engine with dedicated 1k mac addresses ? full duplex ieee 802.3x and half-duplex back pressure flow control ? comprehensive led support ? 7-wire sni support for legacy mac interface ? automatic mdi/mdi-x crossover for plug-and-play ? disable automatic mdi/mdi-x option ? low power: core: 1.8v digital i/o: 3.3v analog i/o: 2.5v or 3.3v ? 0.18m cmos technology ? commercial temperature range: 0c to +70c ? industrial temperature range: ?40c to +85c ? available in 128-pin pqfp package applications ? broadband gateway/firewall/vpn ? integrated dsl or cable modem multi-port router ? wireless lan access point plus gateway ? home networking expansion ? standalone 10/100 switch ? hotel/campus/mxu gateway ? enterprise voip gateway/phone ? fttx customer premise equipment ? managed media converter ordering information part number standard pb-free temperature range package ks8995ma ksz8995ma 0c to +70c 128-pin pqfp ks8995fq ksz8995fq 0c to +70c 128-pin pqfp ks8995mai ksz8995mai ?40c to +85c 128-pin pqfp KS8995FQI ksz8995fqi ?40c to +85c 128-pin pqfp
micrel, inc. ks8995ma/fq semptember 2008 4 m9999-091508 revision history revision date summary of changes 2.0 10/10/03 created. 2.1 10/30/03 editorial changes on electrical characteristics. 2.2 4/01/04 editorial changes on the ttl input and output el ectrical characteristics. 2.3 1/19/05 insert recommended reset ci rcuit, pg. 70. editorial, pg. 36. 2.4 4/13/05 changed vddio to 3.3v. changed jitter to 16 ns max. 2.5 2/6/06 added pb-free opti on for industrial version. 2.6 7/12/06 add a note for vlan table write, improve the timing diagram for mii interface, update pin description for pcrs, pcol, etc. and update the description of the register bits for the loopback, etc. 2.7 6/01/07 add the package thermal information in the operating rating and the transformer power consumption information in the electrical characteristics note. 2.8 03/20/08 add ksz8995fq information and pin description. 2.9 09/15/08 add ksz8995fq block diagram and descriptions for revision id and led mode.
micrel, inc. ks8995ma/fq semptember 2008 5 m9999-091508 contents system level applications...................................................................................................... ..................................... 8 pin confi guration .............................................................................................................. .......................................... 10 pin description (by number).................................................................................................... .................................. 11 pin description (by na me) ...................................................................................................... ................................... 17 introduc tion ................................................................................................................... .............................................. 23 functional overview: physi cal layer tr ansceiver ................................................................................ .................. 23 100base-tx tr ansmit............................................................................................................ .................................. 23 100base-tx re ceive............................................................................................................. .................................. 23 pll clock synthesizer.......................................................................................................... .................................... 23 scrambler/de-scrambl er (100base-tx only)....................................................................................... ................... 24 100base-fx o peration........................................................................................................... ................................. 24 100base-fx signal detection .................................................................................................... ............................. 24 100base-fx far end f ault ....................................................................................................... ................................. 24 10base-t tr ansmit .............................................................................................................. .................................... 24 10base-t re ceive ............................................................................................................... .................................... 24 power mana gement............................................................................................................... ................................... 24 mdi/mdi-x auto crossover ....................................................................................................... ............................... 24 auto-negot iation ............................................................................................................... ........................................ 24 functional overview : switch core ............................................................................................... ............................. 25 address look-up ................................................................................................................ ...................................... 25 learning ....................................................................................................................... ............................................. 25 migration ...................................................................................................................... ............................................. 25 aging .......................................................................................................................... ............................................... 25 forwarding ..................................................................................................................... ........................................... 25 switching engine ............................................................................................................... ....................................... 26 media access controll er (mac) o peration........................................................................................ ....................... 26 inter-packet gap (ipg) ............................................................................................................................... .............. 26 backoff algorithm ............................................................................................................................... ....................... 26 late collision ............................................................................................................................... ............................. 26 illegal frames ............................................................................................................................... ............................ 26 flow control ............................................................................................................................... ............................... 26 half-duplex back pressure ........................................................................................................................... 28 broadcast storm protection ............................................................................................................................... ....... 28 mii interface operation ........................................................................................................ ..................................... 29 sni interface operation ........................................................................................................ .................................... 31 advanced func tionality......................................................................................................... ..................................... 31 spanning tree support.......................................................................................................... ................................... 31 special t agging mo de ........................................................................................................... ................................... 32 igmp support ................................................................................................................... ........................................ 33 port mirror ing support......................................................................................................... ...................................... 34 vlan support ................................................................................................................... ........................................ 34 rate limi t support ............................................................................................................. ....................................... 35 configuration interf ace........................................................................................................ ...................................... 36 i 2 c master serial bus configuration ......................................................................................................................... 38 spi slave serial bus configuration .......................................................................................................................... 38 mii management inte rface (miim) ................................................................................................ ............................ 41 register de scription ........................................................................................................... ........................................ 42 global regi sters ............................................................................................................... ........................................ 43 register 0 (0x00): chip id0 ............................................................................................................................... ....... 43 register 1 (0x01): ch ip id1 / start switch ................................................................................................................ 43 register 2 (0x02): global control 0 .......................................................................................................................... 43 register 3 (0x03): global control 1 .......................................................................................................................... 43 register 4 (0x04): global control 2 .......................................................................................................................... 44 register 5 (0x05): global control 3 .......................................................................................................................... 45
micrel, inc. ks8995ma/fq semptember 2008 6 m9999-091508 register 6 (0x07): global control 4 .......................................................................................................................... 46 register 7 (0x07): global control 5 .......................................................................................................................... 46 register 8 (0x08): global control 6 .......................................................................................................................... 46 register 9 (0x09): global control 7 .......................................................................................................................... 46 register 10 (0x0a): global control 8 ........................................................................................................................ 47 register 11 (0x0b): global control 9 ........................................................................................................................ 47 port registers ................................................................................................................. .......................................... 48 register 16 (0x10): port 1 control 0 ......................................................................................................................... 48 register 17 (0x11): port 1 control 1 ......................................................................................................................... 49 register 18 (0x12): port 1 control 2 ......................................................................................................................... 49 register 19 (0x13): port 1 control 3 ......................................................................................................................... 50 register 20 (0x14): port 1 control 4 ......................................................................................................................... 50 register 21 (0x15): port 1 control 5 ......................................................................................................................... 51 register 22 (0x16): port 1 control 6 ......................................................................................................................... 51 register 23 (0x17): port 1 control 7 ......................................................................................................................... 51 register 24 (0x18): port 1 control 8 ......................................................................................................................... 51 register 25 (0x19): port 1 control 9 ......................................................................................................................... 52 register 26 (0x1a): port 1 control 10 ....................................................................................................................... 52 register 27 (0x1b): port 1 control 11 ....................................................................................................................... 52 register 28 (0x1c): port 1 control 12 ...................................................................................................................... 53 register 29 (0x1d): port 1 control 13 ...................................................................................................................... 54 register 30 (0x1e): port 1 status 0 .......................................................................................................................... 54 register 31 (0x1f): port 1 control 14 ....................................................................................................................... 55 advanced contro l registers ..................................................................................................... ................................ 55 register 96 (0x60): tos priority control register 0 ................................................................................................ 55 register 97 (0x61): tos priority control register 1 ................................................................................................ 55 register 98 (0x62): tos priority control register 2 ................................................................................................ 55 register 99 (0x63): tos priority control register 3 ................................................................................................ 55 register 100 (0x64): tos priority control register 4 .............................................................................................. 55 register 101 (0x65): tos priority control register 5 .............................................................................................. 56 register 102 (0x66): tos priority control register 6 .............................................................................................. 56 register 103 (0x67): tos priority control register 7 .............................................................................................. 56 register 104 (0x68): mac address register 0 ......................................................................................................... 56 register 105 (0x69): mac address register 1 ......................................................................................................... 56 register 106 (0x6a): mac address register 2 ........................................................................................................ 56 register 107 (0x6b): mac address register 3 ........................................................................................................ 56 register 108 (0x6c): mac address register 4 ........................................................................................................ 56 register 109 (0x6d): mac address register 5 ....................................................................................................... 56 register 110 (0x6e): indirect access control 0 ........................................................................................................ 56 register 111 (0x6f): indirect access control 1 ........................................................................................................ 56 register 112 (0x70): indirect data register 8 .......................................................................................................... 56 register 113 (0x71): indirect data register 7 .......................................................................................................... 57 register 114 (0x72): indirect data register 6 .......................................................................................................... 57 register 115 (0x73): indirect data register 5 .......................................................................................................... 57 register 116 (0x74): indirect data register 4 .......................................................................................................... 57 register 117 (0x75): indirect data register 3 .......................................................................................................... 57 register 118 (0x76): indirect data register 2 .......................................................................................................... 57 register 119 (0x77): indirect data register 1 .......................................................................................................... 57 register 120 (0x78): indirect data register 0 .......................................................................................................... 57 register 121 (0x79): digital testing status 0 ........................................................................................................... 57 register 122 (0x7a): digital testing status 1 ........................................................................................................... 57 register 123 (0x7b): digital testing control 0 ......................................................................................................... 57 register 124 (0x7c): digital testing control 1 ......................................................................................................... 57 register 125 (0x7d): analog testing control 0 ........................................................................................................ 57 register 126 (0x7e): analog testing control 1 ........................................................................................................ 57 register 127 (0x7f): analog testing status ............................................................................................................. 57
micrel, inc. ks8995ma/fq semptember 2008 7 m9999-091508 static m ac addr ess ............................................................................................................. ....................................... 58 vlan addr ess ................................................................................................................... .......................................... 60 dynamic mac address............................................................................................................ ................................... 61 mib counters ................................................................................................................... ............................................ 62 miim regi sters ................................................................................................................. ............................................ 65 register 0: mii cont rol ........................................................................................................ ...................................... 65 register 1: mii status ......................................................................................................... ...................................... 65 register 2: phyid high......................................................................................................... .................................. 66 register 3: phyid low .......................................................................................................... ................................. 66 register 4: adve rtisement ability .............................................................................................. ................................ 66 register 5: link partner ability ............................................................................................... .................................. 66 absolute maximum ratings (1) ............................................................................................................................... ..... 67 operating ratings (2) ............................................................................................................................... ..................... 67 electrical characteristics (4, 5) ............................................................................................................................... ....... 67 timing di agrams ................................................................................................................ ......................................... 69 selection of isolation transformer (1) ......................................................................................................................... 77 package info rmation ............................................................................................................ ....................................... 78
micrel, inc. ks8995ma/fq semptember 2008 8 m9999-091508 system level applications ethernet mac cpu switch controller on-chip frame buffers mii-sw 10/100 phy 5 4-port lan mii-p5 1-port wan i/f 10/100 mac 1 10/100 mac 2 10/100 mac 3 10/100 mac 4 10/100 mac 5 10/100 phy 1 10/100 phy 2 10/100 phy 3 10/100 phy 4 spi/gpio spi ethernet mac external wan port phy not required. figure 1. broadband gateway ethernet mac cpu switch controller on-chip frame buffers mii-sw 10/100 phy 5 4-port lan mii-p5 10/100 mac 1 10/100 mac 2 10/100 mac 3 10/100 mac 4 10/100 mac 5 10/100 phy 1 10/100 phy 2 10/100 phy 3 10/100 phy 4 wan phy & afe (xdsl, cm...) spi spi/gpio figure 2. integrated broadband router
micrel, inc. ks8995ma/fq semptember 2008 9 m9999-091508 switch controller on-chip frame buffers 10/100 phy 5 5-port lan 10/100 mac 1 10/100 mac 2 10/100 mac 3 10/100 mac 4 10/100 mac 5 10/100 phy 1 10/100 phy 2 10/100 phy 3 10/100 phy 4 figure 3. standalone switch figure 4. usi ng ksz8995fq for dual media converter or fiber daisy chain connection
micrel, inc. ks8995ma/fq semptember 2008 10 m9999-091508 pin configuration 128-pin pqfp
micrel, inc. ks8995ma/fq semptember 2008 11 m9999-091508 pin description (by number) pin number pin name type (1) port pin function (2) 1 mdi-xdis lpd 1-5 disable auto mdi/mdi-x. pd (default) = normal operation. pu = disable auto mdi/mdi-x on all ports. 2 gnda gnd analog ground. 3 vddar p 1.8v analog v dd . 4 rxp1 i 1 physical receive signal + (differential). 5 rxm1 i 1 physical receive signal ? (differential). 6 gnda gnd analog ground. 7 txp1 o 1 physical transmit signal + (differential). 8 txm1 o 1 physical transmit signal ? (differential). 9 vddat p 2.5v or 3.3v analog v dd . 10 rxp2 i 2 physical receive signal + (differential). 11 rxm2 i 2 physical receive signal ? (differential). 12 gnda gnd analog ground. 13 txp2 o 2 physical transmit signal + (differential). 14 txm2 o 2 physical transmit signal ? (differential). 15 vddar p 1.8v analog v dd . 16 gnda gnd analog ground. 17 iset set physical transmit output current. pull-down with a 3.01k ? 1% resistor. 18 vddat p 2.5v or 3.3v analog v dd . 19 rxp3 i 3 physical receive signal + (differential). 20 rxm3 i 3 physical receive signal - (differential). 21 gnda gnd analog ground. 22 txp3 o 3 physical transmit signal + (differential). 23 txm3 o 3 physical transmit signal ? (differential). 24 vddat p 2.5v or 3.3v analog v dd . 25 rxp4 i 4 physical receive signal + (differential). 26 rxm4 i 4 physical receive signal - (differential). 27 gnda gnd analog ground. 28 txp4 o 4 physical transmit signal + (differential). 29 txm4 o 4 physical transmit signal ? (differential). 30 gnda gnd analog ground. notes: 1. p = power supply. i = input. o = output. i/o = bidirectional. gnd = ground. ipu = input w/internal pull-up. ipd = input w/internal pull-down. ipd/o = input w/internal pull-down during reset, output pin otherwise. ipu/o = input w/internal pull-up during reset, output pin otherwise. nc = no connect. 2. pu = strap pin pull-up. pd = strap pull-down.
micrel, inc. ks8995ma/fq semptember 2008 12 m9999-091508 pin number pin name type (1) port pin function 31 vddar p 1.8v analog v dd . 32 rxp5 i 5 physical receive signal + (differential). 33 rxm5 i 5 physical receive signal ? (differential). 34 gnda gnd analog ground. 35 txp5 o 5 physical transmit signal + (differential). 36 txm5 o 5 physical transmit signal ? (differential). 37 vddat p 2.5v or 3.3v analog v dd . 38 fxsd5/fxsd3 ipd 5/3 fiber signal detect pin. fxsd5 is for port 5 of the ks8995ma. fxsd3 is for port 3 of the ks8995fq 39 fxsd4 ipd 4 fiber signal detect pin for port 4. 40 gnda gnd analog ground. 41 vddar p 1.8v analog v dd . 42 gnda gnd analog ground. 43 vddar p 1.8v analog v dd . 44 gnda gnd analog ground. 45 mux1 nc factory test pins. mux1 and mux2 should be left unconnected for normal operation mode mux1 mux2 46 mux2 nc normal operation nc nc 47 pwrdn_n ipu full-chip power down. active low. 48 reserve nc reserved pin. no connect. 49 gndd gnd digital ground. 50 vddc p 1.8v digital core v dd . 51 pmtxen ipd 5 phy[5] mii transmit enable. 52 pmtxd3 ipd 5 phy[5] mii transmit bit 3. 53 pmtxd2 ipd 5 phy[5] mii transmit bit 2. 54 pmtxd1 ipd 5 phy[5] mii transmit bit 1. 55 pmtxd0 ipd 5 phy[5] mii transmit bit 0. 56 pmtxer ipd 5 phy[5] mii transmit error. 57 pmtxc o 5 phy[5] mii transmit clock. phy mode mii. 58 gndd gnd digital ground. 59 vddio p 3.3v digital v dd for digital i/o circuitry. 60 pmrxc o 5 phy[5] mii receive clock. phy mode mii. notes: 1. p = power supply. i = input. o = output. i/o = bidirectional. gnd = ground. ipu = input w/internal pull-up. ipd = input w/internal pull-down. ipd/o = input w/internal pull-down during reset, output pin otherwise. ipu/o = input w/internal pull-up during reset, output pin otherwise. nc = no connect.
micrel, inc. ks8995ma/fq semptember 2008 13 m9999-091508 pin number pin name type (1) port pin function (2) 61 pmrxdv ipd/o 5 phy[5] mii receive data valid. 62 pmrxd3 ipd/o 5 phy[5] mii receive bit 3. strap option: pd (default) = enable flow control; pu = disable flow control. 63 pmrxd2 ipd/o 5 phy[5] mii receive bit 2. strap opt ion: pd (default) = disable back pressure; pu = enable back pressure. 64 pmrxd1 ipd/o 5 phy[5] mii receive bit 1. strap opt ion: pd (default) = drop excessive collision packets; pu = does not drop excessive collision packets. 65 pmrxd0 ipd/o 5 phy[5] mii receive bit 0. strap option: pd (default) = disable aggressive back-off algorithm in half-duplex mode; pu = enable for performance enhancement. 66 pmrxer ipd/o 5 phy[5] mii receive error. strap opt ion: pd (default) = packet size 1518/1522 bytes; pu = 1536 bytes. 67 pcrs ipd/o 5 phy[5] mii carrier sense/strap option for port 4 only. pd (default) = force half-duplex if auto-negotiation is disabl ed or fails. pu = force full-duplex if auto negotiation is disabled or fails. refer to register 76. 68 pcol ipd/o 5 phy[5] mii collision detect/ strap opti on for port 4 only. pd (default) = no force flow control, normal operation. pu = force flow control. refer to register 66 69 smtxen ipd switch mii transmit enable. 70 smtxd3 ipd switch mii transmit bit 3. 71 smtxd2 ipd switch mii transmit bit 2. 72 smtxd1 ipd switch mii transmit bit 1. 73 smtxd0 ipd switch mii transmit bit 0. 74 smtxer ipd switch mii transmit error. 75 smtxc i/o switch mii transmit clock. input in mac mode, output in phy mode mii. 76 gndd gnd digital ground. 77 vddio p 3.3v digital v dd for digital i/o circuitry. 78 smrxc i/o switch mii receive clock. input in mac mode, output in phy mode mii. 79 smrxdv ipd/o switch mii receive data valid. 80 smrxd3 ipd/o switch mii receive bit 3. strap option: pd (default) = disable switch mii full-duplex flow control; pu = enable switch mii full-duplex flow control. 81 smrxd2 ipd/o switch mii receive bit 2. strap option: pd (default) = switch mii in full- duplex mode; pu = switch mii in half-duplex mode. notes: 1. p = power supply. i = input. o = output. i/o = bidirectional. gnd = ground. ipu = input w/internal pull-up. ipd = input w/internal pull-down. ipd/o = input w/internal pull-down during reset, output pin otherwise. ipu/o = input w/internal pull-up during reset, output pin otherwise. nc = no connect. 2. pu = strap pin pull-up. pd = strap pull-down.
micrel, inc. ks8995ma/fq semptember 2008 14 m9999-091508 pin number pin name type (1) port pin function (2) 82 smrxd1 ipd/o switch mii receive bit 1. strap opti on: pd (default) = switch mii in 100mbps mode; pu = switch mii in 10mbps mode. switch mii receive bit 0; strap option: led mode pd (default) = mode 0; pu = mode 1. see ?register 11.? mode 0, link at 100/full ledx[2,1,0]=0,0,0 100/half ledx[2,1,0]=0,1,0 10/full ledx[2,1,0]=0,0,1 10/half ledx[2,1,0]=0,1,1 mode 1, link at 100/full ledx[2,1,0]=0,1,0 100/half ledx[2,1,0]=0,1,1 10/full ledx[2,1,0]=1,0,0 10/half ledx[2,1,0]=1,0,1 mode 0 mode 1 ledx_2 lnk/act 100lnk/act ledx_1 fulld/col 10lnk/act 83 smrxd0 ipd/o ledx_0 speed full duplex 84 scol ipd/o switch mii collision detect. 85 scrs ipd/o switch mode carrier sense. 86 sconf1 ipd dual mii configuration pin. for t he switch mii, ksz8995ma supports both mac mode and phy mode, ksz8995fq supports phy mode only. pin# (91, 86, 87): switch mii phy [5] mii 000 disable, otri disable, otri 001 phy mode mii disable, otri 010 mac mode mii disable, otri 011 phy mode sni disable, otri 100 disable disable 101 phy mode mii phy mode mii 110 mac mode mii phy mode mii 111 phy mode sni phy mode mii 87 sconf0 ipd dual mii configuration pin. 88 gndd gnd digital ground. 89 vddc p 1.8v digital core v dd . 90 led5-2 ipu/o 5 led indicator 2. strap option: agi ng setup. see ?aging? section. pu (default) = aging enable; pd = aging disable. 91 led5-1 ipu/o 5 led indicator 1. strap option: pu ( default): enable phy[5] mii i/f. pd: tristate all phy[5] mii output. see ?pin 86 sconf1.? notes: 1. p = power supply. i = input. o = output. i/o = bidirectional. gnd = ground. ipu = input w/internal pull-up. ipd = input w/internal pull-down. ipd/o = input w/internal pull-down during reset, output pin otherwise. ipu/o = input w/internal pull-up during reset, output pin otherwise. nc = no connect. 2. pu = strap pin pull-up. pd = strap pull-down. otri = output tristated. fulld = full duplex
micrel, inc. ks8995ma/fq semptember 2008 15 m9999-091508 pin number pin name type (1) port pin function 92 led5-0 ipu/o 5 led indicator 0. 93 led4-2 ipu/o 4 led indicator 2. 94 led4-1 ipu/o 4 led indicator 1. 95 led4-0 ipu/o 4 led indicator 0. 96 led3-2 ipu/o 3 led indicator 2. 97 led3-1 ipu/o 3 led indicator 1. 98 led3-0 ipu/o 3 led indicator 0. 99 gndd gnd digital ground. 100 vddio p 3.3v digital v dd for digital i/o. 101 led2-2 ipu/o 2 led indicator 2. 102 led2-1 ipu/o 2 led indicator 1. 103 led2-0 ipu/o 2 led indicator 0. 104 led1-2 ipu/o 1 led indicator 2. 105 led1-1 ipu/o 1 led indicator 1. 106 led1-0 ipu/o 1 led indicator 0. 107 mdc ipu all switch or phy[ 5] mii management data clock. 108 mdio i/o all switch or phy[5] mii management data i/o. features internal pull down to define pin state when not driven. 109 spiq otri all (1) spi serial data output in spi sl ave mode; (2) output clock at 61khz in i 2 c master mode. see ?pin 113.? 110 spic/scl i/o all (1) input clock up to 5mhz in spi slave mode; (2) output clock at 61khz in i 2 c master mode. see ?pin 113.? 111 sspid/sda i/o all (1) serial data input in spi slave mode; (2) serial data input/output in i 2 c master mode. see ?pin 113.? 112 spis_n ipu all active low. (1) spi data transfer st art in spi slave mode. when spis_n is high, the ks8995ma/fq is deselected and spiq is held in high impedance state, a high-to-low trans ition to initiate the spi data transfer; (2) not used in i 2 c master mode. serial bus configuration pin. for this case, if the eeprom is not present, the ks8995ma/fq will start itself with the ps[1.0] = 00 default register values. pin configuration seri al bus configuration ps[1.0]=00 i 2 c master mode for eeprom ps[1.0]=01 reserved ps[1.0]=10 spi slave mode for cpu interface 113 ps1 ipd ps[1.0]=11 factory test mode (bist) notes: 1. p = power supply. i = input. o = output. i/o = bidirectional. gnd = ground. ipu = input w/internal pull-up. ipd = input w/internal pull-down. ipd/o = input w/internal pull-down during reset, output pin otherwise. ipu/o = input w/internal pull-up during reset, output pin otherwise. nc = no connect.
micrel, inc. ks8995ma/fq semptember 2008 16 m9999-091508 pin number pin name type (1) port pin function 114 ps0 ipd serial bus configuration pin. see ?pin 113.? 115 rst_n ipu reset the ks8995ma/fq. active low. 116 gndd gnd digital ground. 117 vddc p 1.8v digital core v dd . 118 testen ipd nc for normal operation. factory test pin. 119 scanen ipd nc for normal operation. factory test pin. 120 nc nc no connect. 121 x1 i 25mhz crystal clock connection/or 3.3v tolerant oscillator input. oscillator should be 100ppm. 122 x2 o 25mhz crystal clock connection. 123 vddap p 1.8v analog v dd for pll. 124 gnda gnd analog ground. 125 vddar p 1.8v analog v dd . 126 gnda gnd analog ground. 127 gnda gnd analog ground. 128 test2 nc nc for normal operation. factory test pin. notes: 1. p = power supply. i = input. o = output. i/o = bidirectional. gnd = ground. ipu = input w/internal pull-up. ipd = input w/internal pull-down. ipd/o = input w/internal pull-down during reset, output pin otherwise. ipu/o = input w/internal pull-up during reset, output pin otherwise. nc = no connect.
micrel, inc. ks8995ma/fq semptember 2008 17 m9999-091508 pin description (by name) pin number pin name type (1) port pin function 39 fxsd4 i 4 fiber signal detect/factory test pin. 38 fxsd3/fxsd5 i 3/5 fiber signal detect/factory test pin for fq or ma 124 gnda gnd analog ground. 42 gnda gnd analog ground. 44 gnda gnd analog ground. 2 gnda gnd analog ground. 16 gnda gnd analog ground. 30 gnda gnd analog ground. 6 gnda gnd analog ground. 12 gnda gnd analog ground. 21 gnda gnd analog ground. 27 gnda gnd analog ground. 34 gnda gnd analog ground. 40 gnda gnd analog ground. 120 nc nc no connect. 127 gnda gnd analog ground. 126 gnda gnd analog ground. 49 gndd gnd digital ground. 88 gndd gnd digital ground. 116 gndd gnd digital ground. 58 gndd gnd digital ground. 76 gndd gnd digital ground. 99 gndd gnd digital ground. 17 iset set physical transmit output current. pull-down with a 3.01k ? 1% resistor. 106 led1-0 ipu/o 1 led indicator 0. 105 led1-1 ipu/o 1 led indicator 1. 104 led1-2 ipu/o 1 led indicator 2. 103 led2-0 ipu/o 2 led indicator 0. 102 led2-1 ipu/o 2 led indicator 1. 101 led2-2 ipu/o 2 led indicator 2. 98 led3-0 ipu/o 3 led indicator 0. notes: 1. p = power supply. i = input. o = output. i/o = bidirectional. gnd = ground. ipu = input w/internal pull-up. ipd = input w/internal pull-down. ipd/o = input w/internal pull-down during reset, output pin otherwise. ipu/o = input w/internal pull-up during reset, output pin otherwise. nc = no connect.
micrel, inc. ks8995ma/fq semptember 2008 18 m9999-091508 pin number pin name type (1) port pin function (2) 97 led3-1 ipu/o 3 led indicator 1. 96 led3-2 ipu/o 3 led indicator 2. 95 led4-0 ipu/o 4 led indicator 0. 94 led4-1 ipu/o 4 led indicator 1. 93 led4-2 ipu/o 4 led indicator 2. 92 led5-0 ipu/o 5 led indicator 0. 91 led5-1 ipu/o 5 led indicator 1. strap option: pu (default) = enable phy mii i/f pd: tristate all phy mii output. see ?pin 86 sconf1.? 90 led5-2 ipu/o 5 led indicator 2. strap option: agi ng setup. see ?aging? section. (default) = aging enable; pd = aging disable. 107 mdc ipu all switch or phy[ 5] mii management data clock. 108 mdio i/o all switch or phy[5] mii management data i/o. 1 mdi-xdis ipd 1-5 disable auto mdi/mdi-x. 45 mux1 nc factory test pins. mux1 and mux2 should be left unconnected for normal operation. 46 mux2 nc mode mux1 mux2 normal operation nc nc 68 pcol ipd/o 5 phy[5] mii collision detect/force flow control. see ?register 18.? for port 4 only. pd (default) = no force flow control. pu = force flow control. 67 pcrs ipd/o 5 phy[5] mii carrier sense/force duplex mode. see ?register 28.? for port 4 only. pd (default) = force half-duplex if auto-negotiation is disabled or fails. pu = force full-dupl ex if auto-negotiation is disabled or fails. 60 pmrxc o 5 phy[5] mii receive clock. phy mode mii. 65 pmrxd0 ipd/o 5 phy[5] mii receive bit 0. strap option: pd (default) = disable aggressive back-off algorithm in half-duplex mode; pu = enable for performance enhancement. 64 pmrxd1 ipd/o 5 phy[5] mii receive bit 1. strap opt ion: pd (default) = drop excessive collision packets; pu = does not drop excessive collision packets. 63 pmrxd2 ipd/o 5 phy[5] mii receive bit 2. strap opt ion: pd (default) = disable back pressure; pu = enable back pressure. 62 pmrxd3 ipd/o 5 phy[5] mii receive bit 3. strap opt ion: pd (default) = enable flow control; pu = disable flow control. 61 pmrxdv ipd/o 5 phy[5] mii receive data valid. 66 pmrxer ipd/o 5 phy[5] mii receive error. strap opt ion: pd (default) = 1522/1518 bytes; pu = packet size up to 1536 bytes. notes: 1. p = power supply. i = input. o = output. i/o = bidirectional. gnd = ground. ipu = input w/internal pull-up. ipd = input w/internal pull-down. ipd/o = input w/internal pull-down during reset, output pin otherwise. ipu/o = input w/internal pull-up during reset, output pin otherwise. nc = no connect. 2. pu = strap pin pull-up. pd = strap pull-down.
micrel, inc. ks8995ma/fq semptember 2008 19 m9999-091508 pin number pin name type (1) port pin function 57 pmtxc o 5 phy[5] mii transmit clock. phy mode mii. 55 pmtxd0 ipd 5 phy[5] mii transmit bit 0. 54 pmtxd1 ipd 5 phy[5] mii transmit bit 1. 53 pmtxd2 ipd 5 phy[5] mii transmit bit 2. 52 pmtxd3 ipd 5 phy[5] mii transmit bit 3. 51 pmtxen ipd 5 phy[5] mii transmit enable. 56 pmtxer ipd 5 phy[5] mii transmit error. 114 ps0 ipd serial bus configuration pin. see ?pin 113.? 113 ps1 ipd serial bus configuration pin. if eeprom is not present, the ks8995ma/fq will start itself with chip default (00)... pin configuration serial bus configuration ps[1:0]=00 i 2 c master mode for eeprom ps[1:0]=01 reserved ps[1:0]=10 spi slave mode for cpu interface ps[1:0]=11 factory test mode (bist) 47 pwrdn_n ipu full-chip power down. active low. 48 reserve nc reserved pin. no connect. 115 rst_n ipu reset the ks8995ma/fq. active low. 5 rxm1 i 1 physical receive signal ? (differential). 11 rxm2 i 2 physical receive signal ? (differential). 20 rxm3 i 3 physical receive signal ? (differential). 26 rxm4 i 4 physical receive signal ? (differential). 33 rxm5 i 5 physical receive signal ? (differential). 4 rxp1 i 1 physical receive signal + (differential). 10 rxp2 i 2 physical receive signal + (differential). 19 rxp3 i 3 physical receive signal + (differential). 25 rxp4 i 4 physical receive signal + (differential). 32 rxp5 i 5 physical receive signal + (differential). 119 scanen ipd nc for normal oper ation. factory test pin. 84 scol ipd/o switch mii collision detect. 87 sconf0 ipd dual mii configuration pin. notes: 1. p = power supply. i = input. o = output. i/o = bidirectional. gnd = ground. ipu = input w/internal pull-up. ipd = input w/internal pull-down. ipd/o = input w/internal pull-down during reset, output pin otherwise. ipu/o = input w/internal pull-up during reset, output pin otherwise. nc = no connect.
micrel, inc. ks8995ma/fq semptember 2008 20 m9999-091508 pin number pin name type (1) port pin function (2) 86 sconf1 ipd dual mii configuration pin. for t he switch mii, ksz8995ma supports both mac mode and phy mode, ksz8995fq supports phy mode only. pin# (91, 86, 87): switch mii phy [5] mii 000 disable, otri disable, otri 001 phy mode mii disable, otri 010 mac mode mii disable, otri 011 phy mode sni disable, otri 100 disable disable 101 phy mode mii phy mode mii 110 mac mode mii phy mode mii 111 phy mode sni phy mode mii 85 scrs ipd/o switch mode carrier sense. 78 smrxc i/o switch mii receive clock. input in mac mode, output in phy mode mii. switch mii receive bit 0; strap option: led mode pd (default) = mode 0; pu = mode 1. see ?register 11.? mode 0 mode 1 ledx_2 lnk/act 100lnk/act ledx_1 fulld/col 10lnk/act 83 smrxd0 ipd/o ledx_0 speed full duplex 82 smrxd1 ipd/o switch mii receive bit 1. strap opti on: pd (default) = switch mii in 100mbps mode; pu = switch mii in 10mbps mode. 81 smrxd2 ipd/o switch mii receive bit 2. strap option: pd (default) = switch mii in full- duplex mode; pu = switch mii in half-duplex mode. 80 smrxd3 ipd/o switch mii receive bit 3. strap option: pd (default) = disable switch mii full-duplex flow control; pu = enable switch mii full-duplex flow control. 79 smrxdv ipd/o switch mii receive data valid. 75 smtxc i/o switch mii transmit clock. input in mac mode, output in phy mode mii. 73 smtxd0 ipd switch mii transmit bit 0. 72 smtxd1 ipd switch mii transmit bit 1. 71 smtxd2 ipd switch mii transmit bit 2. 70 smtxd3 ipd switch mii transmit bit 3. 69 smtxen ipd switch mii transmit enable. 74 smtxer ipd switch mii transmit error. notes: 1. p = power supply. i = input. o = output. i/o = bidirectional. gnd = ground. ipu = input w/internal pull-up. ipd = input w/internal pull-down. ipd/o = input w/internal pull-down during reset, output pin otherwise. ipu/o = input w/internal pull-up during reset, output pin otherwise. otri = output tristated. nc = no connect. 2. pu = strap pin pull-up. pd = strap pull-down. fulld = full duplex
micrel, inc. ks8995ma/fq semptember 2008 21 m9999-091508 pin number pin name type (1) port pin function 110 spic/scl i/o all (1) input clock up to 5mhz in spi slave mode; (2) output clock at 61khz in i 2 c master mode. see ?pin 113.? 111 sspid/sda i/o all (1) serial data input in spi slave mode; (2) serial data input/output in i 2 c master mode. see ?pin 113.? 109 spiq otri all (1) spi serial data output in spi sl ave mode; (2) output clock at 61khz in i 2 c master mode. see ?pin 113.? 112 spis_n ipu all active low. (1) spi data transfer st art in spi slave mode. when spis_n is high, the ks8995ma/fq is deselected and spiq is held in high impedance state, a high-to-low trans ition to initiate the spi data transfer; (2) not used in i 2 c master mode. 128 test2 nc nc for normal operation. factory test pin. 118 testen ipd nc for normal operation. factory test pin. 8 txm1 o 1 physical transmit signal ? (differential). 14 txm2 o 2 physical transmit signal ? (differential). 23 txm3 o 3 physical transmit signal ? (differential). 29 txm4 o 4 physical transmit signal ? (differential). 36 txm5 o 5 physical transmit signal ? (differential). 7 txp1 o 1 physical transmit signal + (differential). 13 txp2 o 2 physical transmit signal + (differential). 22 txp3 o 3 physical transmit signal + (differential). 28 txp4 o 4 physical transmit signal + (differential). 35 txp5 o 5 physical transmit signal + (differential). 123 vddap p 1.8v analog v dd for pll. 41 vddar p 1.8v analog v dd . 43 vddar p 1.8v analog v dd . 3 vddar p 1.8v analog v dd . 15 vddar p 1.8v analog v dd . 31 vddar p 1.8v analog v dd . 125 vddar p 1.8v analog v dd . 18 vddat p 2.5v or 3.3v analog v dd . 9 vddat p 2.5v or 3.3v analog v dd . 24 vddat p 2.5v or 3.3v analog v dd . 37 vddat p 2.5v or 3.3v analog v dd . 50 vddc p 1.8v digital core v dd . notes: 1. p = power supply. i = input. o = output. i/o = bidirectional. gnd = ground. ipu = input w/internal pull-up. ipd = input w/internal pull-down. ipd/o = input w/internal pull-down during reset, output pin otherwise. ipu/o = input w/internal pull-up during reset, output pin otherwise. otri = output tristated. nc = no connect.
micrel, inc. ks8995ma/fq semptember 2008 22 m9999-091508 pin number pin name type (1) port pin function 89 vddc p 1.8v digital core v dd . 117 vddc p 1.8v digital core v dd . 59 vddio p 3.3v digital v dd for digital i/o circuitry. 77 vddio p 3.3v digital v dd for digital i/o circuitry. 100 vddio p 3.3v digital v dd for digital i/o circuitry. 121 x1 i 25mhz crystal clock connection/or 3.3v tolerant oscillator input. oscillator should be 100ppm. 122 x2 o 25mhz crystal clock connection. notes: 1. p = power supply. i = input. o = output.
micrel, inc. ks8995ma/fq semptember 2008 23 m9999-091508 introduction the ks8995ma/fq contains five 10/100 physical layer transc eivers and five media access control (mac) units with an integrated layer 2 managed switch. the device runs in three modes. the firs t mode is as a five-port integrated switch. the second is as a five-port switch with the fifth port decoupled from the physical po rt. in this mode, access to the fifth mac is provided through a media independent interf ace (mii). this is useful for implementing an integrated broadband router. the third mode uses the dual mii feature to recover the use of the fifth phy. this allows the additional broadband gateway configuration, where t he fifth phy may be accessed through the mii-p5 port. the ks8995ma/fq has the flexibility to reside in a m anaged or unmanaged design. in a managed design, a host processor has complete control of the ks8995ma/fq via the spi bus, or partial control via the mdc/mdio interface. an unmanaged design is achieved th rough i/o strapping or eeprom programming at system reset time. on the media side, the ks8995ma/fq supports ieee 802.3 10base-t, 100base-tx on all ports, and the ks8995ma supports 100base-fx on ports 4 and 5, and the ks8995fq supp orts 100base-fx on ports 3 and 4. the ks8995ma/fq can be used as fully managed 5-port sta ndalone switch or two separate media converters. physical signal transmission and reception are enhanced thro ugh the use of patented analog circuitry that makes the design more efficient and allows for lower power consumption and smaller chip die size. the major enhancements from the ks8995e to the ks8995ma/fq are support for host processor management, a dual mii interface, tag as well as port based vlan, s panning tree protocol support, igmp snooping support, port mirroring support and rate limiting functionality. functional overview: phys ical layer transceiver 100base-tx transmit the 100base-tx transmit function performs parallel-to-seri al conversion, 4b/5b coding, scrambling, nrz-to-nrzi conversion, mlt3 encoding and transmission. the circuit star ts with a parallel-to-serial conversion, which converts the mii data from the mac into a 125mhz serial bit stream . the data and control stream is then converted into 4b/5b coding followed by a scrambler. the serialized data is further converted from nrz-to-nrzi format, and then transmitted in mlt3 current output. the output current is set by an external 1% 3.01k ? resistor for the 1:1 transformer ratio. it has a typical rise/fall time of 4ns and complies with the ansi tp-pmd standard regarding amplitude balance, overshoot, and timing jitter. the wave-s haped 10base-t output is also incorporated into the 100base-tx transmitter. 100base-tx receive the 100base-tx receiver function performs adaptive equaliz ation, dc restoration, ml t3-to-nrzi conversion, data and clock recovery, nrzi-to-nrz conversion, de-scrambli ng, 4b/5b decoding, and serial-to-parallel conversion. the receiving side starts with the equalizati on filter to compensate for inter-symbol interference (isi) over the twisted pair cable. since the amplitude loss and phase distortion is a f unction of the length of the cable, the equalizer has to adjust its characteristics to optimize the performance. in this design, the variable equalizer will make an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization. this is an ongoing process and can self-adjust against environmental changes such as temperature variations. the equalized signal then goes through a dc restoration and data conversion block. the dc restoration circuit is used to compensate for the effect of baseline wan der and improve the dynamic range. the differential data conversion circuit converts the mlt3 format back to nrzi. the slicing threshold is also adaptive. the clock recovery circuit extracts the 125mhz clock from the edges of the nrzi signal. this recovered clock is then used to convert the nrzi signal into the nrz format. the signal is then sent through the de-scrambler followed by the 4b/5b decoder. finally, the nrz serial data is convert ed to the mii format and provided as the input data to the mac. pll clock synthesizer the ks8995ma/fq generates 125mhz, 42mhz, 25mhz, and 10mh z clocks for system timing. internal clocks are generated from an external 25mhz crystal or oscillator.
micrel, inc. ks8995ma/fq semptember 2008 24 m9999-091508 scrambler/de-scrambler (100base-tx only) the purpose of the scrambler is to spread the power spec trum of the signal in order to reduce emi and baseline wander. the data is scrambled through the use of an 11-bi t wide linear feedback shift register (lfsr). this can generate a 2047-bit non-repetitive sequence. the receiver will then de-scramble the incoming data stream with the same sequence at the transmitter. 100base-fx operation 100base-fx operation is very similar to 100base-tx operation except that the scrambler/de-scrambler and mlt3 encoder/decoder are bypassed on transmissi on and reception. in this mode t he auto-negotiation feature is bypassed since there is no standard that su pports fiber auto-negotiation. 100base-fx signal detection the physical port runs in 100base-fx mode if fxsdx >0.6 v for ports 3, 4 (ksz8995fq) or ports 4, 5 (ksz8995ma) only. this signal is internally referenced to 1.25v. the fi ber module interface should be set by a voltage divider such that fxsdx ?h? is above this 1.25v reference, indicating sign al detect, and fxsdx ?l? is below the 1.25v reference to indicate no signal. when fxsdx is below 0.6v then 100base-fx mode is disabled. since there is no auto- negotiation for 100base-fx mode, the ports must be forced to ei ther full or half-duplex for the fiber ports. note that strap-in options exist to set duplex mode for port 4, but not for port 3, 5. 100base-fx far end fault far end fault occurs when the signal detection is logically fa lse from the receive fiber module. when this occurs, the transmission side signals the other end of the link by sending 84 1s followed by a zero in the idle period between frames. the far end fault may be disabled through register settings. 10base-t transmit the output 10base-t driver is incor porated into the 100base-t driver to allow transmission with the same magnetics. they are internally wave-shaped and pre-emphas ized into outputs with a typical 2.3v amplitude. the harmonic contents are at least 27db bel ow the fundamental when driven by an all-ones manchester-encoded signal. 10base-t receive on the receive side, input buffer and level detecting squelch ci rcuits are employed. a differential input receiver circuit and a pll perform the decoding function. the manchester-enc oded data stream is separated into clock signal and nrz data. a squelch circuit rejects signals with levels less than 400mv or with short pulsewidths in order to prevent noises at the rxp or rxm input from falsely triggering t he decoder. when the input exceeds the squelch limit, the pll locks onto the incoming signal and the ks8995ma/fq dec odes a data frame. the receiver clock is maintained active during idle periods in between data reception. power management the ks8995ma/fq features a per port pow er down mode. to save power the user can power down ports that are not in use by setting port control registers or mii control re gisters. in addition, it also supports full chip power down mode. when activated, the entire chip will be shutdown. mdi/mdi-x auto crossover the ks8995ma/fq supports mdi/mdi-x auto crossover. this facilitates the use of either a straight connection cat- 5 cable or a crossover cat-5 cable. the auto-sense fu nction will detect remote transmit and receive pairs, and correctly assign the transmit and receive pairs from the micr el device. this can be highly useful when end users are unaware of cable types and can also save on an addition al uplink configuration connection. the auto crossover feature may be disabled through the port control registers. auto-negotiation the ks8995ma/fq conforms to the auto-negotiation protocol as described by the 802.3 committee. auto-negotiation allows unshielded twisted pair (utp) link partners to sele ct the best common mode of operation. in auto-negotiation the link partners advertise cap abilities across the link to each other. if auto-negotiation is not supported or the link partner to the ks8995ma/fq is forced to bypass auto-negotia tion, then the mode is set by observing the signal at the receiver. this is known as parallel mode because while the transmitter is sending auto-negotiation
micrel, inc. ks8995ma/fq semptember 2008 25 m9999-091508 advertisements, the receiver is listening for advertisements or a fixed signal protocol. the flow for the link setup is shown in figure 5. start auto negotiation force link setting listen for 10base-t link pulses listen for 100base-tx idles attempt auto-negotiation link mode set bypass auto-negotiation and set link mode link mode set ? parallel operation join flow no yes yes no figure 5. auto-negotiation functional overview: switch core address look-up the internal look-up table stores mac addresses and their associated informati on. it contains a 1k unicast address table plus switching information. the ks8995ma/fq is guar anteed to learn 1k addresses and distinguishes itself from a hash-based look-up table, which depending on the operating environment and probabilities, may not guarantee the absolute number of addresses it can learn. learning the internal look-up engine updates its table with a new entry if the following conditions are met: ? the received packet?s source address ( sa) does not exist in the look-up table. ? the received packet is good; the packet has no receiving errors and is of legal length. the look-up engine inserts the qualified sa into the table, along with the port number and time stamp. if the table is full, the last entry of the table is delet ed first to make room for the new entry. migration the internal look-up engine also monito rs whether a station is moved. if this occurs, it updates the table accordingly. migration happens when the following conditions are met: ? the received packet?s sa is in the table but t he associated source port information is different. ? the received packet is good; the packet has no receiving errors and is of legal length. the look-up engine will updat e the existing record in the table with the new source port information. aging the look-up engine will update the time stamp information of a record whenever the corresponding sa appears. the time stamp is used in the aging process. if a record is not updated for a period of time, the look-up engine will remove the record from the table. the look-up engine constantly performs the aging process and will continuously remove aging records. the aging period is 300 + 75 seconds. this feature can be enabled or disabled through register 3 or by external pull-up or pull-down re sistors on led[5][2]. see ?register 3? section. forwarding the ks8995ma/fq will forward packets us ing an algorithm that is depicted in the following flowcharts. figure 6 shows stage one of the forwarding algorithm where the search engine looks up the vlan id, static table, and
micrel, inc. ks8995ma/fq semptember 2008 26 m9999-091508 dynamic table for the destination address, and comes up with ?port to forward 1? (ptf1). ptf1 is then further modified by the spanning tree, igmp s nooping, port mirroring, and port vlan processes to come up with ?port to forward 2? (ptf2), as shown in figure 7. this is wh ere the packet will be sent. ks8995ma/fq will not forwar d the following packets : ? error packets. these include framing errors, fcs erro rs, alignment errors, and illegal size packet errors. ? 802.3x pause frames. the ks8995ma/fq will intercept these packets and perform the appropriate actions. ? ?local? packets. based on destinat ion address (da) look-up. if the destinat ion port from the look-up table matches the port where the packet was from, the packet is defined as ?local.? switching engine the ks8995ma/fq features a high-performance switching engine to move data to and from the mac?s, packet buffers. it operates in store and forward mode, while the efficient switching mechanism reduces overall latency. the ks8995ma/fq has a 64kb internal frame buffer. this resour ce is shared between all five ports. the buffer sharing mode can be programmed through register 2. see ?regist er 2.? in one mode, ports are allowed to use any free buffers in the buffer pool. in the second mode, each port is only allowed to use 1/5 of the total buffer pool. there are a total of 512 buffers available. each buffer is sized at 128b. media access controller (mac) operation the ks8995ma/fq strictly abides by ieee 802. 3 standards to maximi ze compatibility. inter-packet gap (ipg) if a frame is successfully transmitted, the 96-bit time ipg is measured between the two consecutive mtxen. if the current packet is experiencing collision, the 96-bit ti me ipg is measured from mcrs and the next mtxen. backoff algorithm the ks8995ma/fq implements the ieee std. 802.3 binary exponential back-off algorithm , and optional ?aggressive mode? back off. after 16 collisions, t he packet will be optionally dropped depen ding on the chip configuration in register 3. see ?register 3.? late collision if a transmit packet experiences collisions after 512-bit times of the transmission, the packet will be dropped. illegal frames the ks8995ma/fq discards frames less than 64 bytes and can be programmed to accept frames up to 1536 bytes in register 4. for special applications, the ks8995ma/f q can also be programmed to accept frames up to 1916 bytes in register 4. since the ks8995m a/fq supports vlan tags, the maximum sizing is adjusted when these tags are present. flow control the ks8995ma/fq supports standard 802.3x flow cont rol frames on both transmit and receive sides. on the receive side, if the ks8995ma/fq receives a pause control frame, the ks8995ma/fq will not transmit the next normal frame until the timer, specified in the pause c ontrol frame, expires. if another pause frame is received before the current timer expires, the timer will be updated with the new val ue in the second pause frame. during this period (being flow controlled), only flow control packets from the ks8995ma/fq will be transmitted. on the transmit side, the ks8995ma/fq has intelligent and effici ent ways to determine when to invoke flow control. the flow control is based on availability of the system resources, including available buffers, available transmit queues and available receive queues. the ks8995ma/fq flow controls a port that has just receiv ed a packet if the destination port resource is busy. the ks8995ma/fq issues a flow control frame (xoff), contai ning the maximum pause ti me defined in ieee standard 802.3x. once the resource is freed up, the ks8995ma/fq s ends out the other flow control frame (xon) with zero pause time to turn off the flow control (turn on transmissi on to the port). a hysteresis feature is also provided to prevent over-activation and deactivation of the flow control mechanism. the ks8995ma/fq flow controls all ports if the receive queue becomes full.
micrel, inc. ks8995ma/fq semptember 2008 27 m9999-091508 start vlan id valid? ptf1=null search static table search complete. get ptf1 from static table. dynamic table search search complete. get ptf1 from vlan table. search complete. get ptf1 from dynamic table. ptf1 -search vlan table. -ingress vlan filtering -discard npvid check yes no found not found found not found search based on da or da+fid this search is based on da+fid figure 6. da look-up flowchart ? stage 1 spanning tre e process ptf1 igm p proces s port mirror process port vlan membership check ptf2 -check receiving port's receive enable bit -check destination port's transmit enable bit -check whether packets are special (bpdu or specified) -applied to mac #1 to #4 -mac#5 is reserved for microprocessor -igm p will be forwarded to port 5 -rx mirror -tx mirror -rx or tx mirror -rx and tx mirror figure 7. da resolution flowchart ? stage 2
micrel, inc. ks8995ma/fq semptember 2008 28 m9999-091508 half-duplex back pressure the ks8995ma/fq also provides a half-duplex back pressure option (note: this is not in ieee 802.3 standards). the activation and deactivation conditions are the same as t he ones given for full-duplex mode. if back pressure is required, the ks8995ma/fq sends preambles to defer the other station's transm ission (carrier sense deference). to avoid jabber and excessive def erence as defined in i eee 802.3 standard, after a ce rtain period of time, the ks8995ma/fq discontinues carrier sense but raises it quickly after it drops packets to inhibit other transmissions. this short silent time (no carrier sense) is to prevent other stations from sending out packets and keeps other stations in a carrier sense deferred state. if the port has pa ckets to send during a back pre ssure situation, the carrier- sense-type back pressure is interrupted and those packets are transmitted instead. if there areno more packets to send, carrier-sense-type back pressure becomes active again until switch resources are free. if a collisionoccurs, the binary exponential backoff algorithm is skipped and carrier sense is generated immediately, reducing the chanceof further colliding and maintaining carrier sense to prevent reception of packets.to ensur e no packet loss in 10base-t or 100base-tx half-duplex modes, the user must enable the following: ? aggressive backoff (register 3, bit 0) ? no excessive collision dr op (register 4, bit 3) ? back pressure (register 4, bit 5) these bits are not set as the default be cause this is not the ieee standard. broadcast storm protection the ks8995ma/fq has an intelligent option to protect the swit ch system from receiving t oo many broadcast packets. broadcastpackets are normally forwarded to all ports except the source port and thus us e too many switch resources (bandwidth andavailable space in transmit queues). the ks89 95ma/fq has the option to include ?multicast packets? for storm control. thebroadcast storm ra te parameters are programmed globally and can be enabled or disabled on a per port basis. the rate is basedon a 50ms interval for 10 0bt and a 500ms interval for 10bt. at the beginning of each interval, the counter is cleared to zeroand the rate lim it mechanism starts to count the number of bytes during the interval. the rate definition is described in registers6 and 7. the default setting for registers 6 and 7 is 0x4a (74 decimal). this is equal to a rate of 1%, calculated as follows: 148,800 frames/sec 50ms/interval 1% = 74 frames/interval (approx.) = 0x4a
micrel, inc. ks8995ma/fq semptember 2008 29 m9999-091508 mii interface operation the media independent interface (mii) is specified by t he ieee 802.3 committee and pr ovides a common interface betweenphysical layer and mac layer devices. the ks8995m a/fq provides two such interfaces. the mii-p5 interface is used to connectto the fifth phy, whereas the m ii-sw interface is used to co nnect to the fifth mac. each of these mii interfaces contains twodistinct groups of si gnals, one for transmission and the other for receiving. table 1 describes the signals used in the mii-p5 interface. sni signal description ks8995ma/fq signal mtxen transmit enable pmtxen mtxer transmit error pmtxer mtxd3 transmit data bit 3 pmtxd[3] mtxd2 transmit data bit 2 pmtxd[2] mtxd1 transmit data bit 1 pmtxd[1] mtxd0 transmit data bit 0 pmtxd[0] mtxc transmit clock pmtxc mcol collision detection pcol mcrs carrier sense pcrs mrxdv receive data valid pmrxdv mrxer receive error pmrxer mrxd3 receive data bit 3 pmrxd[3] mrxd2 receive data bit 2 pmrxd[2] mrxd1 receive data bit 1 pmrxd[1] mrxd0 receive data bit 0 pmrxd[0] mrxc receive clock pmrxc mdc management data clock mdc mdio management data i/o mdio table 1. mii ? p5 signals (phy mode)
micrel, inc. ks8995ma/fq semptember 2008 30 m9999-091508 the table 2 shows three connection ways, 1. the first and second columns show the connections for external mac and mii-sw phy mode. 2. the fourth and fifth columns show the conne ctions for external phy and mii-sw mac mode. 3. the second and fifth columns show the back to back connections for two mii-sws of two devices. phy mode connection mac mode connection external mac ks8995ma/fq signal description external phy ks8995ma only signal mtxen smtxen transmit enable mtxen smrxdv mtxer smtxer transmit error mtxer not used mtxd3 smtxd[3] transmit dat a bit 3 mtxd3 smrxd[3] mtxd2 smtxd[2] transmit dat a bit 2 mtxd2 smrxd[2] mtxd1 smtxd[1] transmit dat a bit 1 mtxd1 smrxd[1] mtxd0 smtxd[0] transmit dat a bit 0 mtxd0 smrxd[0] mtxc smtxc transmit clock mtxc smrxc mcol scol collision detection mcol scol mcrs scrs carrier sense mcrs scrs mrxdv smrxdv receive data valid mrxdv smtxen mrxer not used receive error mrxer smtxer mrxd3 smrxd[3] receive dat a bit 3 mrxd3 smtxd[3] mrxd2 smrxd[2] receive dat a bit 2 mrxd2 smtxd[2] mrxd1 smrxd[1] receive dat a bit 1 mrxd1 smtxd[1] mrxd0 smrxd[0] receive dat a bit 0 mrxd0 smtxd[0] mrxc smrxc receive clock mrxc smtxc table 2. mii ? sw signals the mii-p5 interface operates in phy mode only, while the mii-sw interface operates in either mac mode or phy mode for ksz8995ma. the mii-sw interface operates in phy mode only for ksz8995fq. these interfaces are nibble-wide data interfaces and therefore run at 1/4 the network bit rate (not encoded). additional signals on the transmit side indicate when data is valid or when an error occurs during transmission. likewise, the receive side has indicators that convey when the data is valid and without physical layer errors. for half-duplex operation there is a signal that indicates a collision has occurred during transmission. note that the signal mrxer is not provided on the mii-sw interface for phy mode operation and the signal mtxer is not provided on the mii-sw interface for mac mode ope ration. normally mrxer would indicate a receive error coming from the physical layer device. mtxer would indica te a transmit error from t he mac device. these signals are not appropriate for this configuration. for phy mode operation, if the device interfacing with the ks8995ma/fq has an mrxer pin, it should be tied low. for mac mode op eration, if the device inte rfacing with the ks8995ma has an mtxer pin, it should be tied low.
micrel, inc. ks8995ma/fq semptember 2008 31 m9999-091508 sni interface operation the serial network interface (sni) is compatible with some controllers used for network layer protocol processing. this interface can be directly connected to these types of devices. the signals are divided into two groups, one for transmission and the other for reception. the signals involved are described in table 3. sni signal description ks8995ma/fq signal txen transmit enable smtxen txd serial transmit data smtxd[0] txc transmit clock smtxc col collision detection scol crs carrier sense smrxdv rxd serial receive data smrxd[0] rxc receive clock smrxc table 3. sni signals this interface is a bit-wide data interface and therefore runs at the network bit rate (not encoded). an additional signal on the transmit side indicates when data is valid. li kewise, the receive side has an indicator that conveys when the data is valid. for half-duplex operation there is a signal that indi cates a collision has occurred during transmission. advanced functionality spanning tree support port 5 is the designated port for spanning tree support. the other ports (port 1 ? port 4) can be configured in one of the five spanning tree states via ?transmit enable,? ?receive enable,? and ?learning disable? register settings in registers 18, 34, 50, and 66 for ports 1, 2, 3, and 4, respectively. the following description shows the port setting and software actions taken for each of the five spanning tree states. disable state: the port should not forward or receive any packets. learning is disabled. port setting: "transmit enable = 0, re ceive enable = 0, learning disable = 1." software action: the processor should not send any packets to the port. the switch may still send specific packets to the processor (packets that match some ent ries in the static table with ?overrid ing bit? set) and the processor should discard those packets. note: processor is connected to por t 5 via mii interface. address learning is disabled on the port in this state. blocking state: only packets to the proces sor are forwarded. learning is disabled. port setting: "transmit enable = 0, re ceive enable = 0, learning disable = 1" software action: the processor should not send any packets to the port(s) in this state. the processor should program the ?static mac table? with th e entries that it needs to receive (e.g ., bpdu packets). the ?overriding? bit should also be set so that the switch will forward those specific packets to the processor. ad dress learning is disabled on the port in this state. listening state: only packets to and from the pr ocessor are forwarded. learning is disabled. port setting: "transmit enable = 0, re ceive enable = 0, learning disable = 1. "software action: the processor should pr ogram the static mac table with the ent ries that it needs to receive (e.g. bpdu packets). the ?overriding? bit should be set so that the switch will forward those specific packets to the processor. the processor may send packets to the port(s) in this state, see ?special tagging mode? section for details. address learning is disabled on the port in this state.
micrel, inc. ks8995ma/fq semptember 2008 32 m9999-091508 learning state: only packets to and from the pr ocessor are forwarded. learning is enabled. port setting: ?transmit enable = 0, re ceive enable = 0, learning disable = 0.? software action: the processor should program the static mac table with the entries that it needs to receive (e.g., bpdu packets). the ?overriding? bit should be set so that the switch will forward those specific packets to the processor. the processor may send packets to the port(s) in this state, see ?special tagging mode? section for details. address learning is enabled on the port in this state. forwarding state: packets are forwarded and received normally. learning is enabled. port setting: ?transmit enable = 1, re ceive enable = 1, learning disable = 0.? software action: the processor should program the static mac table with the entries that it needs to receive (e.g., bpdu packets). the ?overriding? bit should be set so that the switch will forward those specific packets to the processor. the processor may send packets to the port(s) in this state, see ?special tagging mode? section for details. address learning is enabled on the port in this state. special tagging mode the special tagging mode is designed for spanning tree prot ocol igmp snooping and is flexible for use in other applications. the special tagging mode, similar to 802. 1q, requires software to change network drivers to insert/modify/strip/interpret the special tag. this mode is e nabled by setting both register 11 bit 0 and register 80 bit 2. 802.1q tag format special tag format tpid (tag protocol identifier, 0x8100) + tci stpid (special t ag identifier, 0x8100) + tci 0x810 + 4 bit for ?port mask?) + tci table 4. special tagging mode format the stpid will only be seen and used on the port 5 interface, which should be connected to a processor. packets from the processor to the switch should be tagge d with stpid and the port mask defined as below: ?0001? packet to port 1 only ?0010? packet to port 2 onl y?0100? packet to port 3 only ?1000? packet to port 4 only ?0011? packet broadcast to port 1 and port 2 ...... ?1111? packet broadcast to port 1, 2, 3 and 4. ?0000? normal tag, will use the ks8995ma/fq internal look-up result. normal packets should use this setting. if packets from the processors do not hav e a tag, the ks8995ma/fq will treat t hem as normal packets and an internal look-up will be performed.the ks8995ma/ fq uses a non-zero ?port mask? to bypass the look- up result and override any port setting, regardless of port states (blocking, disable, listening, learning). table 5 shows the egress rules when dealing with stpid.
micrel, inc. ks8995ma/fq semptember 2008 33 m9999-091508 ingress tag field tx port ?tag insertion? tx port ?tag removal? egress action to tag field (0x810+ port mask) 0 0 ? ? ? ? modify tag field to 0x8100. recalculate crc. no change to tci if not null vid. replace vid with ingress (por t 5) port vid if null vid. (0x810+ port mask) 0 1 ? ? ? (stpid + tci) will be removed. padding to 64 bytes if necessary. recalculate crc. (0x810+ port mask) 1 0 ? ? ? ? modify tag field to 0x8100. recalculate crc. no change to tci if not null vid. replace vid with ingress (por t 5) port vid if null vid. (0x810+ port mask) 1 1 ? ? ? ? modify tag field to 0x8100. recalculate crc. no change to tci if not null vid. replace vid with ingress (por t 5) port vid if null vid. not tagged don?t care don?t care determined by the dynamic mac address table. table 5. stpid egress rules (processor to switch port 5) for packets from regular ports (port 1 - port 4) to port 5, the port mask is used to tell the processor which port the packet was received on, defined as: ?0001? from port 1, ?0010? from port 2, ?0100? from port 3, ?1000? from port 4 no values other than the previous four defined should be received in this direction in the special mode. table 6 shows the egress rule for this direction. ingress packets egress action to tag field tagged with 0x8100 + tci ? modify tpid to 0x810 + ?port mask,? which indicates source port. ? no change to tci, if vid is not null. ? replace null vid with ingress port vid. ? recalculate crc. not tagged ? insert tpid to 0x810 + ?port mask,? which indicates source port. ? insert tci with ingress port vid. ? recalculate crc. table 6. stpid egress rules (switch to processor) igmp support there are two parts involved to support ig mp in layer 2. the first part is ?igmp? snooping. the switch will trap igmp packets and forward them only to the processor port. the ig mp packets are identified as ip packets (either ethernet ip packets or ieee 802.3 snap ip packets ) and ip version = 0x4 and protocol number = 0x 2. the second part is ?multicast address insertion? in the static mac table. on ce the multicast address is programmed in the static mac table, the multicast session will be trim med to the subscribed ports, instead of broadcasting to all ports. to enable this feature, set register 5 bit 6 to 1. also ?special tag mode? needs to be enabled, so that the processor knows which port the igmp packet was received on. enable ?special tag mode? by setting both register 11 bit 0 and register 80 bit 2.
micrel, inc. ks8995ma/fq semptember 2008 34 m9999-091508 port mirroring support ks8995ma/fq supports ?port mirror? comprehensively as: 1. ?receive only? mirror on a port. all the packets receiv ed on the port will be mirror ed on the sniffer port. for example, port 1 is programmed to be ?rx sniff,? and por t 5 is programmed to be the ?sniffer port.? a packet, received on port 1, is destined to port 4 after the inte rnal look-up. the ks8995ma/fq will forward the packet to both port 4 and port 5. ks8995ma/fq can optionally fo rward even ?bad? received packets to port 5. 2. ?transmit only? mirror on a port. all the packets transmitted on the port w ill be mirrored on the sniffer port. for example, port 1 is programmed to be ?tx sniff,? and port 5 is programm ed to be the ?sniffer port.? a packet, received on any of the ports, is destined to port 1 afte r the internal look-up. the ks8995ma/fq will forward the packet to both ports 1 and 5. 3. ?receive and transmit? mirror on two ports. all the pa ckets received on port a and transmitted on port b will be mirrored on the sniffer port. to turn on the ?and? featur e, set register 5 bit 0 to 1. for example, port 1 is programmed to be ?rx sniff,? port 2 is programmed to be ?transmit sniff,? and port 5 is programmed to be the ?sniffer port.? a packet, received on port 1, is destined to port 4 after the internal look-up. the ks8995ma/fq will forward the packet to port 4 only, since it does not meet the ?and? condition. a packet, received on port 1, is destined to port 2 after the internal look-up. th e ks8995ma/fq will forward the packet to both port 2 and port 5. multiple ports can be selected to be ?rx sniffed? or ?tx sniffed.? and any port ca n be selected to be the ?sniffer port.? all these per port features can be selected through register 17. vlan support ks8995ma/fq supports 16 active vlans out of 4096 possible vlans specified in ieee 802.1q. ks8995ma/fq provides a 16-entry vlan table, whic h converts vid (12 bits) to fid (4 bi ts) for address look-up. if a non-tagged or null-vid-tagged packet is received, the ingress port vid is used for look-up. in the vlan mode, the look-up process starts with vlan table look-up to determine whether the vid is valid. if the vid is not valid, the packet will be dropped and its address will not be learned. if the vid is valid, fi d is retrieved for further lo ok-up. fid+da is used to determine the destination port. fid+sa is used for learning purposes. da found in static mac table use fid flag? fid match? da+fid found in dynamic mac table action no don?t care don?t care no broadcast to the membership ports defined in the vlan table bit [20:16]. no don?t care don?t care yes send to the destination port defined in the dynamic mac table bit [54:52]. yes 0 don?t care don?t care send to the destination port(s) defined in the static mac table bit [52:48]. yes 1 no no broadcast to the membership ports defined in the vlan table bit [20:16]. yes 1 no yes send to the destination port defined in the dynamic mac table bit [54:52]. yes 1 yes don?t care send to the destination port(s) defined in the static mac table bit [52:48]. table 7. fid+da look-up in the vlan mode
micrel, inc. ks8995ma/fq semptember 2008 35 m9999-091508 sa+fid found in dynamic mac table action no the sa+fid will be learned into the dynamic table. yes time stamp will be updated. table 8. fid+sa look-up in the vlan mode advanced vlan features are also supported in ks8995ma/ fq, such as ?vlan ingress filtering? and ?discard non pvid? defined in register 18 bit 6 and bit 5. these features can be controlled on a port basis. rate limit support ks8995ma/fq supports hardware rate limiting on ?receive? and ?transmit? independently on a per port basis. it also supports rate limiting in a priority or non-priority environm ent. the rate limit starts from 0kbps and goes up to the line rate in steps of 32kbps. the ks8995ma/fq uses one seco nd as an interval. at the beginning of each interval, the counter is cleared to zero, and the rate limit mechanism st arts to count the number of bytes during this interval. for receive, if the number of bytes exceeds the programmed limit, the switch will stop receiving packets on the port until the ?one second? interval expires. there is an option provided for flow control to prevent packet loss. if the rate limit is programmed greater than or equal to 128kbps and t he byte counter is 8k bytes below the limit, the flow control will be triggered. if the rate limit is programmed lower than 128kbps and the byte counter is 2k bytes below the limit, the flow control will be triggered. for transmit, if the number of bytes exceeds the programmed limit, the switch will stop transmitting packets on the port until the ?one second? interval expires. if priority is enabled, the ks8995ma/fq can support different rate controls for both high priority and low priority packets. this can be programmed through registers 21?27.
micrel, inc. ks8995ma/fq semptember 2008 36 m9999-091508 configuration interface the ks8995ma/fq can function as a managed switch or unmanaged switch. if no eeprom or micro-controller exists, the ks8995ma/fq will operate from its default setti ng. some default settings are configured via strap in options as indicated in the table below. pin # pin name pu/pd (1) description (1) 1 mdi-xdis ipd disable auto mdi/mdi-x. pd = (default) = normal operation pu = disable auto mdi/mdi-x on all ports. 45 mux1 nc factory test pins. mux1 and mux2 should be left unconnected for normal operation. mode mux1 mux2 46 mux2 nc normal operation nc nc 62 pmrxd3 ipd/o phy[5] mii receive bit 3. strap opt ion: pd (default) = enable flow control; pu = disable flow control. 63 pmrxd2 ipd/o phy[5] mii receive bit 2. strap option: pd (default) = disable back pressure; pu = enable back pressure. 64 pmrxd1 ipd/o phy[5] mii receive bit 1. strap option: pd (default) = drop excessive collision packets; pu = does not drop excessive collision packets. 65 pmrxd0 ipd/o phy[5] mii receive bit 0. stra p option: pd (default) = disable aggressive back- off algorithm in half-duplex mode; pu = enable for performance enhancement. 66 pmrxer ipd/o phy[5] mii receive error. stra p option: pd (default) = 1522/1518 bytes; pu = packet size up to 1536 bytes. 67 pcrs ipd/o phy[5] mii carrier sense/strap opt ion for port 4 only. pd (default) = force half- duplex if auto-negotiation is disabled or fails. pu = force full-duplex if auto- negotiation is disabled or fails. refer to register 76. 68 pcol ipd/o phy[5] mii collision detect/strap opt ion for port 4 only. pd (default) = no force flow control. pu = force flow control. refer to register 66. 80 smrxd3 ipd/o switch mii receive bit 3. strap option: pd (default) = disable switch mii full- duplex flow control; pu = enable switch mii full-duplex flow control. 81 smrxd2 ipd/o switch mii receive bit 2. strap option: pd (default) = switch mii in full-duplex mode; pu = switch mii in half-duplex mode. 82 smrxd1 ipd/o switch mii receive bit 1. stra p option: pd (default) = switch mii in 100mbps mode; pu = switch mii in 10mbps mode. switch mii receive bit 0. strap option: led mode pd (default) = mode 0; pu = mode 1. see ?register 11.? mode 0 mode 1 ledx_2 lnk/act 100lnk/act ledx_1 fulld/col 10lnk/act 83 smrxd0 ipd/o ledx_0 speed fulld notes: 1. nc = no connect. ipd = input w/internal pull-down. ipd/o = input w/internal pull-down during reset, output pin otherwise. fulld = full duplex.
micrel, inc. ks8995ma/fq semptember 2008 37 m9999-091508 pin # pin name pu/pd (1) description (1) dual mii configuration pin. for the switch mii, ksz8995ma supports both mac mode and phy mode, ksz8995fq supports phy mode only. pins 91, 86, 87 switch mii phy [5] mii 000 disable, otri disable, otri 001 phy mode mii disable, otri 010 mac mode mii disable, otri 011 phy mode sni disable, otri 100 disable disable 101 phy mode mii phy mode mii 110 mac mode mii phy mode mii 86 sconf1 ipd 111 phy mode sni phy mode mii 87 sconf0 ipd dual mii configuration pin. 90 led5-2 ipu/o led indicator 2. strap option: aging setup. see ?aging? section pu (default) = aging enable; pd = aging disable. 91 led5-1 ipu/o led indicator 1. strap option: pu (default): enable phy[5] mii i/f. pd: tristate all phy[5] mii output. see ?pin 86 sconf1.? serial bus configuration pin. for this case, if the eeprom is not present, the ks8995ma/fq will start itself with the ps[1:0] = 00 default register values . pin configuration serial bus configuration ps[1:0]=00 i 2 c master mode for eeprom ps[1:0]=01 reserved ps[1:0]=10 spi slave mode for cpu interface 113 ps1 ipd ps[1:0]=11 factory test mode (bist) 114 ps0 ipd serial bus configuration pin. see ?pin 113.? 128 test2 nc nc for normal operation. factory test pin. notes: 1. nc = no connect. ipd = input w/internal pull-down. ipd/o = input w/internal pull-down during reset, output pin otherwise. otri = output tristated.
micrel, inc. ks8995ma/fq semptember 2008 38 m9999-091508 i 2 c master serial bus configuration if a 2-wire eeprom exists, the ks8995ma/fq can perform more advanced features like broadcast storm protection and rate control. the eeprom should have the entire valid configuration data from re gister 0 to register 109 defined in the ?memory map,? except the status register s. after reset, the ks8995ma/fq will start to read all 110 registers sequentially from the eeprom . the configuration access time (t prgm ) is less than 15ms as shown in figure 8. .... .... .... rst_n scl sd a t prgm <15 ms figure 8. ks8995ma/fq eeprom configuration timing diagram to configure the ks8995ma/fq with a pre-configured eeprom use the following steps: 1. at the board level, connect pin 110 on the ks8995ma/fq to the scl pi n on the eeprom. connect pin 111 on the ks8995ma/fq to the sda pin on the eeprom. 2. set the input signals ps[1:0] (pins 113 and 114, respec tively) to ?00.? this puts the ks8995ma/fq serial bus configuration into i 2 c master mode. 3. be sure the board-level reset signal is connected to the ks8995ma/fq reset signal on pin 115 (rst_n). 4. program the contents of the eeprom before placing it on the board with the desired configur ation data. note that the first byte in the eeprom must be ?95? for the lo ading to occur properly. if this value is not correct, all other data will be ignored. 5. place eeprom on the board and power up the board. assert t he active-low board level reset to rst_n on the ks8995ma/fq. after the reset is de-asserted, the ks8995m a/fq will begin reading configuration data from the eeprom. the configurat ion access time (t prgm ) is less than 15ms. note: for proper operation, make sure that pin 47 (pwrdn_n) is not asserted during the reset operation. spi slave serial bus configuration the ks8995ma/fq can also act as an spi slave device. through the spi, the entire feature set can be enabled, including ?vlan,? ?igmp snooping,? ?mib counters,? etc. the external master device can access any register from register 0 to register 127 randomly. the system should configure all the desired settings before enabling the switch in the ks8995ma/fq. to enable the switch, write a "1" to register 1 bit 0. two standard spi commands are supported (00000011 fo r ?read data,? and 00000010 for ?write data?). to speed configuration time, the ks8995ma/fq also supports multiple reads or writes. after a byte is written to or read from the ks8995ma/fq, the internal address counter autom atically increments if the spi slave select signal (spis_n) continues to be driven low. if spis_n is kept lo w after the first byte is read, the next byte at the next address will be shifted out on spiq. if spis_n is kept low after t he first byte is written, bits on the master out slave input (spid) line will be written to the next address. assert ing spis_n high terminates a read or write operation. this means that the spis_n signal must be asserted high and then low again before issuing another command and address. the address counter wraps back to zero once it reaches the highest address. t herefore the entire register set can be written to or read from by issuing a single command and address. the ks8995ma/fq is able to support a 5mhz spi bus. a hi gh performance spi master is recommended to prevent internal counter overflow.
micrel, inc. ks8995ma/fq semptember 2008 39 m9999-091508 to use the ks8995ma/fq spi: 1. at the board level, connect ks8995ma/fq pins as follows: ks8995ma/fq pin number ks8995ma/fq signal name microprocessor signal description 112 spis_n spi slave select 110 spic spi clock 111 spid master out slave input 109 spiq master in slave output table 9. spi connections 2. set the input signals ps[1:0] (pins 113 and 114, respectively ) to ?10? to set the serial configuration to spi slave mode. 3. power up the board and assert a reset signal. after reset wa it 100s, the start switch bit in register 1 will be set to ?0?. configure the desired settings in the ks 8995ma/fq before setting the start register to ?1.' 4. write configuration to registers using a typical spi writ e data cycle as shown in figure 9 or spi multiple write as shown in figure 11. note that data input on spi d is registered on the rising edge of spic. 5. registers can be read and configuration can be verified with a typical spi read data cycle as shown in figure 10 or a multiple read as shown in figure 12. note that read data is registered out of spiq on the falling edge of spic. 6. after configuration is written and verified, write a ?1? to register 1 bit 0 to begin ks8995ma/fq operation.
micrel, inc. ks8995ma/fq semptember 2008 40 m9999-091508 spiq spic spid spis_n 00000010 x a7 a6 a5 a4 a3 a2 a1 a0 write command write address write data d2 d0 d1 d3 d4 d5 d6 d7 figure 9. spi write data cycle spiq spic spid spis_n 00000011 x a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 read command read address read data figure 10. spi read data cycle
micrel, inc. ks8995ma/fq semptember 2008 41 m9999-091508 spiq spic spid spis_n 00000010 x a7 a6 a5 a4 a3 a2 a1 a0 write command write address byte 1 d2 d0 d1 d3 d4 d5 d6 d7 spiq spic spid spis_n d7 d6 d5 d4 d4 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 byte 2 byte 3 ... byte n d2 d0 d1 d3 d4 d5 d6 d7 figure 11. spi multiple write spiq spic spid spis_n 00000011 x a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 read command read address byte 1 xxxxxxxx xxxxxxx x byte 2 byte 3 ... byte n x x x x x x x x xxxxxxxx d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 spiq spic spid spis_n figure 12. spi multiple read mii management interface (miim) a standard miim interface is provided for all five ph y devices in the ks8995ma/fq. an external device with mdc/mdio capability is able to read phy status or to conf igure phy settings. the device is able to meet ieee specification of 2.5mhz m dc clock. for details on the miim interf ace standard please re ference the ieee 802.3 specification (section 22.2.4.5). the miim interface does not have access to all the configuration registers in the ks8995ma/fq. it can only access the standard mii registers. se e ?miim registers.? the spi interface, on the other hand, can be used to access the entire ks8995ma/fq feature set.
micrel, inc. ks8995ma/fq semptember 2008 42 m9999-091508 register description offset decimal hex description 0-1 0x00-0x01 chip id registers 2-11 0x02-0x0b global control registers 12-15 0x0c-0x0f reserved 16-29 0x10-0x1d port 1 control registers 30-31 0x1e-0x2f port 1 status registers 32-45 0x20-0x2d port 2 control registers 46-47 0x2e-0x2f port 2 status registers 48-61 0x30-0x3d port 3 control registers 62-63 0x3e-0x3f port 3 status registers 64-77 0x40-0x4d port 4 control registers 78-79 0x4e-0x4f port 4 status registers 80-93 0x50-0x5d port 5 control registers 94-95 0x5e-0x5f port 5 status registers 96-103 0x60-0x67 tos priority control registers 104-109 0x68-0x6d mac address registers 110-111 0x6e-0x6f indirect access control registers 112-120 0x70-0x78 indirect data registers 121-122 0x79-0x7a digital te sting status registers 123-124 0x7b-0x7c digital testing control registers 125-126 0x7d-0x7e analog testing control registers 127 0x7f analog testing status register
micrel, inc. ks8995ma/fq semptember 2008 43 m9999-091508 global registers address name description mode default register 0 (0x00): chip id0 7-0 family id chip family. ro 0x95 register 1 (0x01): chip id1 / start switch 7-4 chip id 0x0 is assigned to m series. (95ma) ro 0x0 3-1 revision id revision id ro based on real chip revision. 0x02=b2, 0x03=b3, 0x04=b4, 0x05=b5, etc. 0 start switch 1, start the chip when external pins (ps1, ps0) = (1,0) or (0,1). note: in (ps1,ps0) = (0,0) mode, the chip will start automatically, after trying to read the external eeprom. if eeprom does not exist, the chip will use default values for all internal registers. if eeprom is present, the contents in the eeprom will be checked. the switch will check: (1) register 0 = 0x95, (2) register 1 [7:4] = 0x0. if this check is ok, the contents in the eeprom will override chip register default values =0, chip will not start when external pins (ps1, ps0) = (1,0) or (0,1). note: (ps1, ps0) = (1,1) for factory test only. rw 0x0 register 2 (0x02): global control 0 7 reserved reserved. r/w 0x0 6-4 802.1p base priority used to classi fy priority for incoming 802.1q packets ?user priority? is compared against this value : classified as high priority. < : classified as low priority. r/w 0x4 3 enable phy mii 1, enable phy mii-p5 interface. note: if not enabled, the switch will tri-state all outputs. r/w pin led5-1 strap option. pull-down (0): isolate. pull-up (1): enable. note: led[5][1] has internal pull- up. 2 buffer share mode 1, buffer pool is shared by all ports. a port can use more buffer when other ports are not busy. 0, a port is only allowed to use 1/5 of the buffer pool. r/w 0x1 1 unh mode 1, the switch will dr op packets with 0x8808 in t/l filed, or da=01-80-c2-00-00-01. 0, the switch will drop packets qualified as ?flow control? packets. r/w 0 0 link change age 1, link change from ?link? to ?no link? will cause fast aging (<800s) to age address table faster. after an age cycle is complete, the age logic will return to normal (300 + 75 seconds ). note: if any port is unplugged, all addresses will be automatically aged out. r/w 0 register 3 (0x03): global control 1 7 pass all frames 1, switch all packets including bad ones. used solely for debugging purpose. works in conjunction with sniffer mode. r/w 0 6 reserved reserved. r/w 0
micrel, inc. ks8995ma/fq semptember 2008 44 m9999-091508 address name description mode default 5 ieee 802.3x transmit flow control disable 0, will enable transmit flow control based on an result. 1, will not enable transmit flow control regardless of an result. r/w pin pmrxd3 strap option. pull-down(0): enable tx flow control. pull-up(1): disable tx/rx flow control. note: pmrxd3 has internal pull- down. 4 ieee 802.3x receive flow control disable 0, will enable receive flow control based on an result. 1, will not enable receive flow control regardless of an result. note: bit 5 and bit 4 default values are controlled by the same pin, but they can be programmed independently. r/w pin pmrxd3 strap option. pull-down (0): enable rx flow control. pull-up (1): disable tx/rx flow control. note: pmrxd3 has internal pull- down. 3 frame length field check 1, will check frame length field in the ieee packets if the actual length does not match, the packet will be dropped (for l/t <1500) . r/w 0 2 aging enable 1, enable age function in the chip. 0, disable aging function. r/w pin led[5][2] strap option. pull- down (0): aging disable pull-up (1): aging enable. note: led[5][2] has internal pull up. 1 fast age enable 1 = turn on fast age (800s). r/w 0 0 aggressive back off enable 1 = enable more aggressive back-off algorithm in half duplex mode to enhance performance. this is not an ieee standard. r/w pin pmrxd0 strap option. pull- down (0): disable aggressive back off. pull-up (1): aggressive back off. note: pmrxd0 has internal pull down. register 4 (0x04): global control 2 7 unicast port-vlan mismatch discard this feature is used for port vlan (described in register 17, register 33...). 1, all packets can not cross vlan boundary. 0, unicast packets (excluding unknown/ multicast/broadcast) can cross vlan boundary. r/w 1 6 multicast storm protection disable 1, ?broadcast storm protection? does not include multicast packets. only da=ffffffffffff packets will be regulated. 0, ?broadcast storm protection? includes da = ffffffffffff and da[40] = 1 packets. r/w 1 5 back pressure mode 1, carrier sense based backpressure is selected. 0, collision based backpressure is selected. r/w 1
micrel, inc. ks8995ma/fq semptember 2008 45 m9999-091508 address name description mode default 4 flow control and back pressure fair mode 1, fair mode is selected. in th is mode, if a flow control port and a non-flow control port talk to the same destination port, packets from the non-flow control port may be dropped. this is to prevent the flow control port from being flow controlled for an extended period of time. 0, in this mode, if a flow control port and a non-flow control port talk to the same destination port, the flow control port will be flow controlled. this may not be ?fair? to the flow control port. r/w 1 3 no excessive collision drop 1, the swit ch will not drop packets when 16 or more collisions occur. 0, the switch will drop packets when 16 or more collisions occur. r/w pin pmrxd1 strap option. pull- down (0): drop excessive collision packets. pull-up (1): don?t drop excessive collision packets. note: pmrxd1 has internal pull down. 2 huge packet support 1, will accept packet sizes up to 1916 bytes (inclusive). this bit setting will override setting from bit 1 of the same register. 0, the max packet size will be determined by bit 1 of this register. r/w 0 1 legal maximum packet size check disable 1, will accept packet sizes up to 1536 bytes (inclusive). 0, 1522 bytes for tagged packets (not including packets with stpid from cpu to ports 1-4), 1518 bytes for untagged packets. any packets larger than the specified value will be dropped. r/w pin pmrxer strap option. pull-down (0): 1518/1522 byte packets. pull-up (1): 1536 byte packets. note: pmrxer has internal pull- down. 0 priority buffer reserve 1, each output queue is pre-allocated 48 buffers, used exclusively for high priority packets. it is recommended to enable this when priority queue feature is turned on. 0, no reserved buffers for high priority packets. r/w 0 register 5 (0x05): global control 3 7 802.1q vlan enable 1, 802.1q vlan m ode is turned on. vlan table needs to set up before the operation. 0, 802.1q vlan is disabled. r/w 0 6 igmp snoop enable on switch mii interface 1, igmp snoop enabled. all the igmp packets will be forwarded to switch mii port. 0, igmp snoop disabled. r/w 0 5 enable direct mode on switch mii interface 1, direct mode on port 5. this is a special mode for the switch mii interface. usi ng preamble before mrxdv to direct switch to forward packets, bypassing internal look- up. 0, normal operation. r/w 0 4 enable pre-tag on switch mii interface 1, packets forwarded to switch mii interface will be pre-tagged with the source port number (preamble before mrxdv). 0, normal operation. r/w 0 3-2 priority scheme select 00 = always deliver high priority packets first. 01 = deliver high/low packets at ratio 10/1. 10 = deliver high/low packets at ratio 5/1. 11 = deliver high/low packets at ratio 2/1. r/w 00
micrel, inc. ks8995ma/fq semptember 2008 46 m9999-091508 address name description mode default 1 enable ?tag? mask 1, the last 5 digi ts in the vid field are used as a mask to determine which port(s) the packet should be forwarded to. 0, no tag masks. r/w 0 0 sniff mode select 1, will do rx and tx sniff (both source port and destination port need to match). 0, will do rx or tx sniff (either source port or destination port needs to match). this is the mode used to implement rx only sniff. r/w 0 register 6 (0x07): global control 4 7 switch mii back pressure enable 1, enable half-duplex back pressure on switch mii interface. 0, disable back pressure on switch mii interface. r/w 0 6 switch mii half-duplex mode 1, enable mii interface half-duplex mode. 0, enable mii interface full-duplex mode. r/w pin smrxd2 strap option. pull- down (0): full- duplex mode. pull- up (1): half-duplex mode. note: smrxd2 has internal pull-down. 5 switch mii flow control enable 1, enable full-duplex flow contro l on switch mii interface. 0, disable full-duplex flow cont rol on switch mii interface. r/w pin smrxd3 strap option. pull-down (0): disable flow control. pull-up(1): enable flow control. note: smrxd3 has internal pull- down. 4 switch mii 10bt 1, the switch interface is in 10mbps mode. 0, the switch interface is in 100mbps mode. r/w pin smrxd1 strap option. pull- down (0): enable 100mbps. pull-up (1): enable 10mpbs. note: smrxd1 has internal pull- down. 3 null vid replacement 1, will replace null vid with port vid (12 bits). 0, no replacement for null vid. r/w 0 2-0 broadcast storm protection rate bit [10:8] this along with the next register determines how many ?64 byte blocks? of packet data allowed on an input port in a preset period. the period is 50ms for 100bt or 500ms for 10bt. the default is 1%. r/w 000 register 7 (0x07): global control 5 7-0 broadcast storm protection rate bit [7:0] this along with the previous register determines how many ?64 byte blocks? of packet data are allowed on an input port in a preset period. the period is 50ms for 100bt or 500ms for 10bt. the default is 1%. r/w 0x4a (1) register 8 (0x08): global control 6 7-0 factory testing reserved r/w 0x24 register 9 (0x09): global control 7 7-0 factory testing reserved r/w 0x28 note: 1. 148,800 frames/sec 50ms/interval 1% = 74 frames/interval (approx.) = 0x4a.
micrel, inc. ks8995ma/fq semptember 2008 47 m9999-091508 address name description mode default register 10 (0x0a): global control 8 7-0 factory testing reserved r/w 0x24 register 11 (0x0b): global control 9 7-4 reserved n/a 0 3 phy power save 1 = disable phy power save mode. 0 = enable phy power save mode. r/w 0 2 factory setting reserved r/w 0 0 = led mode 0. 1 = led mode 1. mode 0, link at 100/full ledx[2,1,0]=0,0,0 100/half ledx[2,1,0]=0,1,0 10/full ledx[2,1,0]=0,0,1 10/half ledx[2,1,0]=0,1,1 mode 1, link at 100/full ledx[2,1,0]=0,1,0 100/half ledx[2,1,0]=0,1,1 10/full ledx[2,1,0]=1,0,0 10/half ledx[2,1,0]=1,0,1 (0=led on, 1=led off) r/w pin smrxd- strap option. pull- down(0): enabled led mode 0. pull- up(1): enabled led mode 1. note: smpxd0 has internal pull- down 0. mode 0 mode 1 ledx_2 lnk/act 100lnk/act ledx_1 fulld/col 10lnk/act 1 led mode ledx_0 speed fulld 0 special tipd mode 1 = enable special tag mode. 0 = disable special tag mode. r/w 0
micrel, inc. ks8995ma/fq semptember 2008 48 m9999-091508 port registers the following registers are used to enabl e features that are assigned on a per port basis. the register bit assignments are the same for all ports, but the addres s for each port is different, as indicated. register 16 (0x10): port 1 control 0 register 32 (0x20): port 2 control 0 register 48 (0x30): port 3 control 0 register 64 (0x40): port 4 control 0 register 80 (0x50): port 5 control 0 address name description mode default 7 broadcast storm protection enable 1, enable broadcast storm protection for ingress packets on the port. 0, disable broadcast storm protection. r/w 0 6 diffserv priority classification enable 1, enable diffserv priority classification for ingress packets on port. 0, disable diffserv function. r/w 0 5 802.1p priority classification enable 1, enable 802.1p priority classification for ingress packets on port. 0, disable 802.1p. r/w 0 4 port-based priority classification enable 1, ingress packets on the port will be classified as high priority if ?diffserv? or ?802.1p? classification is not enabled or fails to classify. 0, ingress packets on port will be classified as low priority if ?diffserv? or ?802.1p? classification is not enabled or fails to classify. note: ?diffserv?, ?802.1p? and port priority can be enabled at the same time. the or?ed result of 802.1p and dscp overwrites the port priority. r/w 0 3 reserved reserved r/w 0 2 tag insertion 1, when packets ar e output on the port, the switch will add 802.1q tags to packets without 802.1q tags when received. the switch will not add tags to packets already tagged. the tag inserted is the ingress port?s ?port vid.? 0, disable tag insertion. r/w 0 1 tag removal 1, when packets ar e output on the port, the switch will remove 802.1q tags from packets with 802.1q tags when received. the switch will not modify packets received without tags. 0, disable tag removal. r/w 0 0 priority enable 1, the port output queue is split into high and low priority queues. 0, single output queue on the port. there is no priority differentiation even though packets are classified into high or low priority. r/w 0
micrel, inc. ks8995ma/fq semptember 2008 49 m9999-091508 register 17 (0x11): port 1 control 1 register 33 (0x21): port 2 control 1 register 49 (0x31): port 3 control 1 register 65 (0x41): port 4 control 1 register 81 (0x51): port 5 control 1 address name description mode default 7 sniffer port 1, port is designated as sniffer port and will transmit packets that are monitored. 0, port is a normal port. r/w 0 6 receive sniff 1, all the packets received on the port will be marked as ?monitored packets? and forwarded to the designated ?sniffer port.? 0, no receive monitoring. r/w 0 5 transmit sniff 1, all the packets transmitted on the port will be marked as ?monitored packets? and forwarded to the designated ?sniffer port.? 0, no transmit monitoring. r/w 0 4-0 port vlan membership define the port?s port vlan membership. bit 4 stands for port 5, bit 3 for port 4...bit 0 for port 1. the port can only communicate within the membership. a ?1? includes a port in the membership, a ?0? excludes a port from membership. r/w 0x1f register 18 (0x12): port 1 control 2 register 34 (0x22): port 2 control 2 register 50 (0x32): port 3 control 2 register 66 (0x42): port 4 control 2 register 82 (0x52): port 5 control 2 address name description mode default 7 reserved reserved 0x0 6 ingress vlan filtering. 1, the sw itch will discard packates whose vid port membership in vlan table bit[20:16] does not include the ingress port. 0, no ingress vlan filtering. r/w 0 5 discard non-pvid packets 1, the switch will discard packets whose vid does not match ingress port default vid. 0, no packets will be discarded. r/w 0 4 force flow control 1, will always enable rx and tx flow control on the port, regardless of an result. 0, the flow control is enabled based on an result. r/w 0 for port 4 only, there is a special configuration pin to set the default, pin pcol strap option. pull-down (0): no force flow control. pull-up (1): force flow control. note: pcol has internal pull-down .
micrel, inc. ks8995ma/fq semptember 2008 50 m9999-091508 address name description mode default 3 back pressure enable 1, enable port half-duplex back pressure. 0, disable port half-duplex back pressure. r/w pin pmrxd2 strap option. pull- down (0): disable back pressure. pull-up(1): enable back pressure. note: pmrxd2 has internal pull- down. 2 transmit enable 1, enable packet transmission on the port. 0, disable packet transmission on the port. r/w 1 1 receive enable 1, enable packet reception on the port. 0, disable packet reception on the port. r/w 1 0 learning disable 1, disable switch address learning capability. 0, enable switch address learning. r/w 0 note: bits 2-0 are used for spanning tree s upport. see ?spanning tree support? section. register 19 (0x13): port 1 control 3 register 35 (0x23): port 2 control 3 register 51 (0x33): port 3 control 3 register 67 (0x43): port 4 control 3 register 83 (0x53): port 5 control 3 address name description mode default 7-0 default tag [15:8] port ?s default tag, containing: 7-5: user priority bits 4: cfi bit 3-0 : vid[11:8] r/w 0 register 20 (0x14): port 1 control 4 register 36 (0x24): port 2 control 4 register 52 (0x34): port 3 control 4 register 68 (0x44): port 4 control 4 register 84 (0x54): port 5 control 4 address name description mode default 7-0 default tag [7:0] default port 1?s tag, containing: 7-0: vid[7:0] r/w 1 note: registers 19 and 20 (and those corresponding to other ports) se rve two purposes: (1) associated with the ingress untagged packe ts, and used for egress tagging; (2) default vid for the ingress untagged or null-vid-tagged packets, and used for address look up.
micrel, inc. ks8995ma/fq semptember 2008 51 m9999-091508 register 21 (0x15): port 1 control 5 register 37 (0x25): port 2 control 5 register 53 (0x35): port 3 control 5 register 69 (0x45): port 4 control 5 register 85 (0x55): port 5 control 5 address name description mode default 7-0 transmit high priority rate control [7:0] this along with port control 7, bits [3:0] form a 12-bit field to determine how many ?32kbps? high priority blocks can be transmitted (in a unit of 4k bytes in a one second period). r/w 0 register 22 (0x16): port 1 control 6 register 38 (0x26): port 2 control 6 register 54 (0x36): port 3 control 6 register 70 (0x46): port 4 control 6 register 86 (0x56): port 5 control 6 address name description mode default 7-0 transmit low priority rate control [7:0] this along with port control 7, bits [7:4] form a 12-bit field to determine how many ?32kbps? low priority blocks can be transmitted (in a unit of 4k bytes in a one second period). r/w 0 register 23 (0x17): port 1 control 7 register 39 (0x27): port 2 control 7 register 55 (0x37): port 3 control 7 register 71 (0x47): port 4 control 7 register 87 (0x57): port 5 control 7 address name description mode default 7-4 transmit low priority rate control [11:8] this along with port control 6, bits [7:0] form a 12-bit field to determine how many ?32kbps? low priority blocks can be transmitted (in a unit of 4k bytes in a one second period). r/w 0 3-0 transmit high priority rate control [11:8] this along with port control 5, bits [7:0] form a 12-bit field to determine how many ?32kbps? high priority blocks can be transmitted (in unit of 4k bytes in a one second period). r/w 0 register 24 (0x18): port 1 control 8 register 40 (0x28): port 2 control 8 register 56 (0x38): port 3 control 8 register 72 (0x48): port 4 control 8 register 88 (0x58): port 5 control 8 address name description mode default 7-0 receive high priority rate control [7:0] this along with port control 10, bits [3:0] form a 12-bit field to determine how many ?32kbps? high priority blocks can be received (in a unit of 4k bytes in a one second period). r/w 0
micrel, inc. ks8995ma/fq semptember 2008 52 m9999-091508 register 25 (0x19): port 1 control 9 register 41 (0x29): port 2 control 9 register 57 (0x39): port 3 control 9 register 73 (0x49): port 4 control 9 register 89 (0x59): port 5 control 9 address name description mode default 7-0 receive low priority rate control [7:0] this along with port control 10, bits [7:4] form a 12-bit field to determine how many ?32kbps? low priority blocks can be received (in a unit of 4k bytes in a one second period). r/w 0 register 26 (0x1a): port 1 control 10 register 42 (0x2a): port 2 control 10 register 58 (0x3a): port 3 control 10 register 74 (0x4a): port 4 control 10 register 90 (0x5a): port 5 control 10 address name description mode default 7-4 receive low priority rate control [11:8] this along with port control 9, bits [7:0] form a 12-bit field to determine how many ?32kbps? low priority blocks can be received (in a unit of 4k bytes in a one second period). r/w 0 3-0 receive high priority rate control [11:8] this along with port control 8, bits [7:0] form a 12-bit field to determine how many ?32kbps? high priority blocks can be received (in a unit of 4k bytes in a one second period). r/w 0 register 27 (0x1b): port 1 control 11 register 43 (0x2b): port 2 control 11 register 59 (0x3b): port 3 control 11 register 75 (0x4b): port 4 control 11 register 91 (0x5b): port 5 control 11 address name description mode default 7 receive differential priority rate control 1, if bit 6 is also ?1? this will enable receive rate control for this port on low priority packets at the low priority rate. if bit 5 is also ?1?, th is will enable receive rate control on high priority packets at the high priority rate. 0, receive rate control will be based on the low priority rate for all packets on this port. r/w 0 6 low priority receive rate control enable 1, enable port?s low priority receive rate control feature. 0, disable port?s low priority receive rate control. r/w 0 5 high priority receive rate control enable 1, if bit 7 is also ?1? this will enable the port?s high priority receive rate control feature. if bit 7 is a ?0? and bit 6 is a ?1?, all receive packets on this port will be rate controlled at the low priority rate. 0, disable port?s high priority receive rate control feature. r/w 0 4 low priority receive rate flow control enable 1, flow control may be asserted if the port?s low priority receive rate is exceeded. 0, flow control is not asserted if the port?s low priority receive rate is exceeded. r/w 0
micrel, inc. ks8995ma/fq semptember 2008 53 m9999-091508 address name description mode default 3 high priority receive rate flow control enable 1, flow control may be asserted if the port?s high priority receive rate is exceeded. to use this, differential receive rate control must be on. 0, flow control is not asserted if the port?s high priority receive rate is exceeded. r/w 0 2 transmit differential priority rate control 1, transmit rate control on both high and low priority packets based on the rate counters defined by the high and low priority packets respectively. 0, transmit rate control on any packets. the rate counters defined in low priority will be used. r/w 0 1 low priority transmit rate control enable 1, enable the port?s low priority transmit rate control feature. 0, disable the port?s low priority transmit rate control feature. r/w 0 0 high priority transmit rate control enable 1, enable the port?s high priority transmit rate control feature. 0, disable the port?s high priority transmit rate control feature. r/w 0 register 28 (0x1c): port 1 control 12 register 44 (0x2c): port 2 control 12 register 60 (0x3c): port 3 control 12 register 76 (0x4c): port 4 control 12 register 92 (0x5c): port 5 control 12 address name description mode default 7 disable auto-negotiation 1, disable auto-negotiation, speed and duplex are decided by bit 6 and 5 of the same register. 0, auto-negotiation is on. r/w 0 6 forced speed 1, forced 100bt if an is disabled (bit 7). 0, forced 10bt if an is disabled (bit 7). r/w 1 5 forced duplex 1, forced full-duplex if (1) an is disabled or (2) an is enabled but failed. 0, forced half-duplex if (1) an is disabled or (2) an is enabled but failed. r/w 0 for port 4 only, there is a special configure pin to set the default pin pcrs strap option. pull-down (0): force half- duplex. pull-up (1): force full- duplex. note: pcrs has internal pull down . 4 advertised flow control capability 1, advertise flow control capability. 0, suppress flow control capability from transmission to link partner. r/w 1 3 advertised 100bt full- duplex capability 1, advertise 100bt full-duplex capability. 0, suppress 100bt full-duplex capability from transmission to link partner. r/w 1 2 advertised 100bt half- duplex capability 1, advertise 100bt half-duplex capability. 0, suppress 100bt half-duplex capability from transmission to link partner. r/w 1 1 advertised 10bt full- duplex capability 1, advertise 10bt full-duplex capability. 0, suppress 10bt full-duplex capability from transmission to link partner. r/w 1
micrel, inc. ks8995ma/fq semptember 2008 54 m9999-091508 address name description mode default 0 advertised 10bt half- duplex capability 1, advertise 10bt half-duplex capability. 0, suppress 10bt half-duplex capability from transmission to link partner. r/w 1 note: port control 12 and 13, and port status 0 contents can be accessed by miim (mdc/mdio) interface via the standard miim register definition. register 29 (0x1d): port 1 control 13 register 45 (0x2d): port 2 control 13 register 61 (0x3d): port 3 control 13 register 77 (0x4d): port 4 control 13 register 93 (0x5d): port 5 control 13 address name description mode default 7 led off 1, turn off all port?s leds (ledx_2, ledx_1, ledx_0, where ?x? is the port number). these pins will be driven high if this bit is set to one. 0, normal operation. r/w 0 6 txids 1, disable port?s transmitter. 0, normal operation. r/w 0 5 restart an 1, restart auto-negot iation. 0 = normal operation. r/w 0 4 disable far end fault 1, disable far end fault detection and pattern transmission. 0, enable far end fault detection and pattern transmission. r/w 0 3 power down 1, power down. 0, normal operation. r/w 0 2 disable auto mdi/mdi-x 1, disable auto mdi/mdi-x function. 0, enable auto mdi/mdi-x function. r/w 0 1 forced mdi 1, if auto mdi/mdi-x is disabled, force phy into mdi mode. 0, mdix mode. r/w 0 0 mac loopback 1, perform mac loopback. 0, normal operation. r/w 0 register 30 (0x1e): port 1 status 0 register 46 (0x2e): port 2 status 0 register 62 (0x3e): port 3 status 0 register 78 (0x4e): port 4 status 0 register 94 (0x5e): port 5 status 0 address name description mode default 7 mdix status 1, mdi. 0, mdi-x. ro 0 6 an done 1, an done. 0, an not done. ro 0 5 link good 1, link good. 0, link not good. ro 0 4 partner flow control capability 1, link partner flow control capable. 0, link partner not flow control capable. ro 0 3 partner 100bt full- duplex capability 1, link partner 100bt full-duplex capable. 0, link partner not 100bt full-duplex capable. ro 0
micrel, inc. ks8995ma/fq semptember 2008 55 m9999-091508 address name description mode default 2 partner 100bt half- duplex capability 1, link partner 100bt half-duplex capable. 0, link partner not 100bt half-duplex capable. ro 0 1 partner 10bt full-duplex capability 1, link partner 10bt full-duplex capable. 0, link partner not 10bt full-duplex capable. ro 0 0 partner 10bt half-duplex capability 1, link partner 10bt half-duplex capable. 0, link partner not 10bt half-duplex capable. ro 0 register 31 (0x1f): port 1 control 14 register 47 (0x2f): port 2 control 14 register 63 (0x3f): port 3 control 14 register 79 (0x4f): port 4 control 14 register 95 (0x5f): port 5 control 14 address name description mode default 7 phy loopback 1, perform phy loopback, i.e. loopback mac?s tx back to rx. 0, normal operation. r/w 0 6 remote loopback 1, perform remo te loopback, i.e. loopback phy?s rx back to tx. 0, normal operation. r/w 0 5 phy isolate 1, electrical isol ation of phy from mii and tx+/tx-. 0, normal operation. r/w 0 4 soft reset 1, phy soft reset. 0, normal operation. r/w 0 3 force link 1, force link in the phy. 0, normal operation. r/w 0 2-1 reserved n/a ro 0 0 far end fault 1, far end fault status detected. 0, no far end fault status detected. ro 0 advanced control registers the ipv4 tos priority control registers implement a fully decoded 64 bit differentiated services code point (dscp) register used to determine priority from the 6 bit tos fiel d in the ip header. the most significant 6 bits of the tos field are fully decoded into 64 po ssibilities, and the singular code that results is compar ed against the corresponding bit in the dscp register. if the register bit is a 1, the priority is high; if it is a 0, the priority is low. address name description mode default register 96 (0x60): tos priority control register 0 7-0 dscp[63:56] r/w 00000000 register 97 (0x61): tos priority control register 1 7-0 dscp[55:48] r/w 00000000 register 98 (0x62): tos priority control register 2 7-0 dscp[47:40] r/w 00000000 register 99 (0x63): tos priority control register 3 7-0 dscp[39:32] r/w 00000000 register 100 (0x64): tos priority control register 4 7-0 dscp[31:24] r/w 00000000
micrel, inc. ks8995ma/fq semptember 2008 56 m9999-091508 address name description mode default register 101 (0x65): tos priority control register 5 7-0 dscp[23:16] r/w 00000000 register 102 (0x66): tos priority control register 6 7-0 dscp[15:8] r/w 00000000 register 103 (0x67): tos priority control register 7 7-0 dscp[7:0] r/w 00000000 registers 104 to 109 define the switching engine?s mac address. th is 48-bit address is used as the source address in mac pause control frames. address name description mode default register 104 (0x68): mac address register 0 7-0 maca[47:40] r/w 0x00 register 105 (0x69): mac address register 1 7-0 maca[39:32] r/w 0x10 register 106 (0x6a): mac address register 2 7-0 maca[31:24] r/w 0xa1 register 107 (0x6b): mac address register 3 7-0 maca[23:16] r/w 0xff register 108 (0x6c): mac address register 4 7-0 maca[15:8] r/w 0xff register 109 (0x6d): mac address register 5 7-0 maca[7:0] r/w 0xff use registers 110 and 111 to read or write data to the static ma c address table, vlan table, dynamic address table, or the mib counters. address name description mode default register 110 (0x6e): indirect access control 0 7-5 reserved reserved. r/w 000 4 read high write low 1, read cycle. 0, write cycle. r/w 0 3-2 table select 00 = static mac address table selected. 01 = vlan table selected. 10 = dynamic address table selected. 11 = mib counter selected. r/w 0 1-0 indirect address high bit 9-8 of indirect address. r/w 00 register 111 (0x6f): indirect access control 1 7-0 indirect address low bit 7- 0 of indirect address. r/w 00000000 note: write to register 111 will actually trigger a command. read or write access will be decided by bit 4 of register 110. address name description mode default register 112 (0x70): indirect data register 8 68-64 indirect data bit 68- 64 of indirect data. r/w 00000
micrel, inc. ks8995ma/fq semptember 2008 57 m9999-091508 address name description mode default register 113 (0x71): indirect data register 7 63-56 indirect data bit 63-56 of indirect data. r/w 00000000 register 114 (0x72): indirect data register 6 55-48 indirect data bit 55-48 of indirect data. r/w 00000000 register 115 (0x73): indirect data register 5 47-40 indirect data bit 47-40 of indirect data. r/w 00000000 register 116 (0x74): indirect data register 4 39-32 indirect data bit 39-32 of indirect data. r/w 00000000 register 117 (0x75): indirect data register 3 31-24 indirect data bit of 31- 24 of indirect data r/w 00000000 register 118 (0x76): indirect data register 2 23-16 indirect data bit 23-16 of indirect data. r/w 00000000 register 119 (0x77): indirect data register 1 15-8 indirect data bit 15-8 of indirect data. r/w 00000000 register 120 (0x78): indirect data register 0 7-0 indirect data bit 7-0 of indirect data. r/w 00000000 do not write or read to/from registers 121 to 127. doing so may prevent proper operation. micrel internal testing only. address name description mode default register 121 (0x79): digital testing status 0 7-0 factory testing reserved . qm_split status ro 0x0 register 122 (0x7a): digital testing status 1 7-0 factory testing reserved. dbg[7:0] ro 0x0 register 123 (0x7b): digital testing control 0 7-0 factory testing rese rved. dbg[12:8] r/w 0x0 register 124 (0x7c): digital testing control 1 7-0 factory testing reserved. r/w 0x0 register 125 (0x7d): analog testing control 0 7-0 factory testing reserved. r/w 0x0 register 126 (0x7e): analog testing control 1 7-0 factory testing reserved. r/w 0x0 register 127 (0x7f): analog testing status 7-0 factory testing reserved. ro 0x0
micrel, inc. ks8995ma/fq semptember 2008 58 m9999-091508 static mac address ks8995ma/fq has a static and a dynamic address table. w hen a da look-up is requested, both tables will be searched to make a packet forwarding decision. when an sa look-up is requested, only the dynamic table is searched for aging, migration, and learning purposes. the stat ic da look-up result will have precedence over the dynamic da look-up result. if there are da matches in both tables, the result fr om the static table will be used. the static table can only be accessed and cont rolled by an external spi master (usu ally a processor). the entries in the static table will not be aged out by ks8995ma/fq. an exter nal device does all addition, modification and deletion. note: register bit assignments are different for st atic mac table reads and static mac table write, as shown in the two tables below. address name description mode default format of static mac table for reads (8 entries) 60-57 fid filter vlan id, representing one of the 16 active vlans ro 0000 56 use fid 1, use (fid+mac) to look-up in static table. 0, use mac only to look-up in static table. ro 0 55 reserved reserved. ro n/a 54 override 1, override spanning tree ?transmit enable = 0? or ?receive enable = 0* setting. this bit is used for spanning tree implementation. 0, no override. ro 0 53 valid 1, this entry is valid, the look-up result will be used. 0, this entry is not valid. ro 0 52-48 forwarding ports the 5 bits c ontrol the forward ports, example: 00001, forward to port 1 00010, forward to port 2 ?.. 10000, forward to port 5 00110, forward to port 2 and port 3 11111, broadcasting (excluding the ingress port) ro 00000 47-0 mac address 48 bit mac address. ro 0x0 format of static mac table for writes (8 entries) 59-56 fid filter vlan id, representing one of the 16 active vlans. w 0000 55 use fid 1, use (fid+mac) to look-up in static table. 0, use mac only to look-up in static table. w 0 54 override 1, override spanning tree ?transmit enable = 0? or ?receive enable = 0? setting. this bit is used for spanning tree implementation. 0, no override. w 0 53 valid 1, this entry is valid, the look-up result will be used. 0, this entry is not valid. w 0 52-48 forwarding ports the 5 bits control the forward ports, example: 00001, forward to port 1 00010, forward to port 2 ..... 10000, forward to port 5 00110, forward to port 2 and port 3 11111, broadcasting (excluding the ingress port) w 00000 47-0 mac address 48-bit mac address. w 0x0 table 10. static mac address table
micrel, inc. ks8995ma/fq semptember 2008 59 m9999-091508 examples: (1) static address table read (read the 2nd entry) write to register 110 with 0x 10 (read static table selected) write to register 111 with 0x1 (trigger the read operation) then read register 113 (60-56) read register 114 (55-48) read register 115 (47-40) read register 116 (39-32) read register 117 (31-24) read register 118 (23-16) read register 119 (15-8) read register 120 (7-0) (2) static address table write (write the 8th entry) write to register 110 with 0x 10 (read static table selected) write register 113 (59-56) write register 114 (55-48) write register 115 (47-40) write register 116 (39-32) write register 117 (31-24) write register 118 (23-16) write register 119 (15-8) write register 120 (7-0) write to register 110 with 0x00 (write static table selected) write to register 111 with 0x7 (trigger the write operation)
micrel, inc. ks8995ma/fq semptember 2008 60 m9999-091508 vlan address the vlan table is used for vlan table look-up. if 802.1q vlan mode is enabled (register 5 bit 7 = 1), this table is used to retrieve vlan information that is associated with the ingress packet. the information includes fid (filter id), vid (vlan id), and vlan membership described below: address name description mode default format of static vlan table (16 entries) 21 valid 1, the entry is valid. 0, entry is invalid. r/w 1 20-16 membership specify which ports are members of the vlan. if a da look-up fails (no match in both static and dynamic tables), the packet associated with this vlan will be forwarded to ports sp ecified in this field. e.g., 11001 means port 5, 4, and 1 are in this vlan. r/w 11111 15-12 fid filter id. ks8995ma/fq supports 16 active vlans represented by these four bi t fields. fid is the mapped id. if 802.1q vlan is enabled, the look-up will be based on fid+da and fid+sa. r/w 0 11-0 vid ieee 802.1q 12 bit vlan id. r/w 1 table 11. vlan table if 802.1q vlan mode is enabled, ks8995ma/fq assigns a vi d to every ingress packet. if the packet is untagged or tagged with a null vid, the packet is assigned with the default port vid of the ingress port. if the packet is tagged with non-null vid, the vid in the tag is used . the look-up process starts from the vlan table look-up. if the vid is not valid, the packet is dropped and no address learning occurs . if the vid is valid, the fid is retrieved. the fid+da and fid+sa lookups are performed. the fid+da look-up determines the forwarding ports. if fid+ da fails, the packet is broadcast to all the members (excluding the ingress por t) of the vlan. if fid+sa fa ils, the fid+sa is learned. examples: (1) vlan table read (read the 3rd entry) write to register 110 with 0x 14 (read vlan table selected) write to register 111 with 0x2 (trigger the read operation) then read register 118 (vlan table bits 21-16) read register 119 (vlan table bits 15-8) read register 120 (vlan table bits 7-0) (2) vlan table write (write the 7th entry) write to register 118 (vlan table bits 21-16) write to register 119 (vlan table bits 15-8) write to register 120 (vlan table bits 7-0) write to register 110 with 0x04 (write vlan table selected) write to register 111 with 0x6 (trigger the write operation) note: the sequence of the writing entries should st art from entry 0. improper sequence of the vlan enties could cause the vlan to be non-functional.
micrel, inc. ks8995ma/fq semptember 2008 61 m9999-091508 dynamic mac address this table is read only. the contents ar e maintained by the ks8995ma/fq only. address name description mode default format of dynamic mac address table (1k entries) 68 mac empty 1, there is no valid entry in the table. 0, there are valid entries in the table. ro 1 67-58 no of valid entries indicates how many valid entries in the table. 0x3ff means 1k entries 0x1 means 2 entries 0x0 and bit 68 = 0: means 1 entry 0x0 and bit 68 = 1: means 0 entry ro 0 57-56 time stamp 2-bit counters for internal aging ro 55 data ready 1, the entry is not r eady, retry until this bit is set to 0. 0, the entry is ready. ro 54-52 source port the source port where fid+mac is learned. 000 port 1 001 port 2 010 port 3 011 port 4 100 port 5 ro 0x0 51-48 fid filter id. ro 0x0 47-0 mac address 48-bit mac address. ro 0x0 table 12. dynamic mac address table examples: (1) dynamic mac address table read (read the 1s t entry), and retrieve the mac table size write to register 110 with 0x18 (read dynamic table selected) write to register 111 with 0x0 (trigger the read operation) then read register 112 (68-64) read register 113 (63-56); // the above two registers show # of entries read register 114 (55-48) // if bit 55 is 1, restart (reread) from this register read register 115 (47-40) read register 116 (39-32) read register 117 (31-24) read register 118 (23-16) read register 119 (15-8) read register 120 (7-0) (2) dynamic mac address table read (read the 257th entr y), without retrieving # of entries information write to register 110 with 0x19 (read dynamic table selected) write to register 111 with 0x1 (trigger the read operation) then read register 114 (55-48) // if bit 55 is 1, restart (reread) from this register read register 115 (47-40) read register 116 (39-32) read register 117 (31-24) read register 118 (23-16) read register 119 (15-8) read register 120 (7-0)
micrel, inc. ks8995ma/fq semptember 2008 62 m9999-091508 mib counters the mib counters are provided on per port basis. the indirect memory is as below: for port 1 offset counter name description 0x0 rxloprioritybyte rx lo-priority (def ault) octet count including bad packets. 0x1 rxhiprioritybyte rx hi-prior ity octet count including bad packets. 0x2 rxundersizepkt rx undersize packets w/good crc. 0x3 rxfragments rx fragment packets w/bad cr c, symbol errors or alignment errors. 0x4 rxoversize rx oversize packets w/good crc (max: 1536 or 1522 bytes). 0x5 rxjabbers rx packets longer than 1522b w/either cr c errors, alignment errors, or symbol errors (depends on max packet size setting) or rx packets longer than 1916b only. 0x6 rxsymbolerror rx packets w/ invalid data symbol and legal preamble, packet size. 0x7 rxcrcerror rx packets within (64,1522) bytes w/an integral number of bytes and a bad crc (upper limit depends on max packet size setting). 0x8 rxalignmenterror rx packets within (64,1522) byte s w/a non-integral number of bytes and a bad crc (upper limit depends on max packet size setting). 0x9 rxcontrol8808pkts the number of mac control fram es received by a port with 88-08h in ethertype field. 0xa rxpausepkts the number of pause frames received by a port. pause frame is qualified with ethertype (88- 08h), da, control opcode (00-01), data length (64b min), and a valid crc. 0xb rxbroadcast rx good broadcast packets (not including errored broadcast packets or valid multicast packets). 0xc rxmulticast rx good multicast packets (not includi ng mac control frames, errored multicast packets or valid broadcast packets). 0xd rxunicast rx good unicast packets. 0xe rx64octets total rx packets (bad packets included) that were 64 octets in length. 0xf rx65to127octets total rx packets (bad packets incl uded) that are between 65 and 127 octets in length. 0x10 rx128to255octets total rx packets (bad packets in cluded) that are between 128 and 255 octets in length. 0x11 rx256to511octets total rx packets (bad packets in cluded) that are between 256 and 511 octets in length. 0x12 rx512to1023octets total rx packets (bad packets in cluded) that are between 512 and 1023 octets in length. 0x13 rx1024to1522octets total rx packets (bad packets in cluded) that are between 1024 and 1522 octets in length (upper limit depends on max packet size setting). 0x14 txloprioritybyte tx lo-priority good octet count, including pause packets. 0x15 txhiprioritybyte tx hi-priority good octet count, including pause packets. 0x16 txlatecollision the number of times a collision is detected later than 512 bit-times into the tx of a packet. 0x17 txpausepkts the number of pause frames transmitted by a port. 0x18 txbroadcastpkts tx good broadcast packets (not in cluding errored broadcast or valid multicast packets). 0x19 txmulticastpkts tx good multicast packets (not includi ng errored multicast packets or valid broadcast packets). 0x1a txunicastpkts tx good unicast packets. 0x1b txdeferred tx packets by a port for which t he 1st tx attempt is delayed due to the busy medium. 0x1c txtotalcollision tx tota l collision, half-duplex only. 0x1d txexcessivecollision a count of frames for which tx fails due to excessive collisions. 0x1e txsinglecollision successfully tx frames on a por t for which tx is inhibited by exactly one collision. 0x1f txmultiplecollision successfully tx frames on a por t for which tx is inhibited by more than one collision. table 13. port-1 mib counter indirect memory offsets
micrel, inc. ks8995ma/fq semptember 2008 63 m9999-091508 for port 2, the base is 0x20, same offset definition (0x20-0x3f) for port 3, the base is 0x40, same offset definition (0x40-0x5f) for port 4, the base is 0x60, same offset definition (0x60-0x7f) for port 5, the base is 0x80, same offset definition (0x80-0x9f) address name description mode default format of per port mib counters (16 entries) 31 overflow 1, counter overflow. 0, no counter overflow. ro 0 30 count valid 1, counter value is valid. 0, counter value is not valid. ro 0 29-0 counter values counter value. ro 0 offset counter name description 0x100 port1 tx drop packets tx packets dropped due to lack of resources. 0x101 port2 tx drop packets tx packets dropped due to lack of resources. 0x102 port3 tx drop packets tx packets dropped due to lack of resources. 0x103 port4 tx drop packets tx packets dropped due to lack of resources. 0x104 port5 tx drop packets tx packets dropped due to lack of resources. 0x105 port1 rx drop packets rx packe ts dropped due to lack of resources. 0x106 port2 rx drop packets rx packe ts dropped due to lack of resources. 0x107 port3 rx drop packets rx packe ts dropped due to lack of resources. 0x108 port4 rx drop packets rx packe ts dropped due to lack of resources. 0x109 port5 rx drop packets rx packe ts dropped due to lack of resources. table 14. all port dropped packet mib counters address name description mode default format of all port dropped packet mib counters 30-16 reserved reserved. n/a n/a 15-0 counter values counter value. ro 0 note: all port dropped packet mib counters do not indicate overflow or va lidity; therefore the application must keep track of overflo w and valid conditions. examples: (1) mib counter read (read port 1 rx 64 counter) write to register 110 with 0x1c (read mib counters selected) write to register 111 with 0x e (trigger the read operation) then read register 117 (counter value 31-24) // if bit 31 = 1, there was a counter overflow // if bit 30 = 0, restart (re read) from this register read register 118 (counter value 23-16) read register 119 (counter value 15-8) read register 120 (counter value 7-0)
micrel, inc. ks8995ma/fq semptember 2008 64 m9999-091508 (2) mib counter read (read port 2 rx 64 counter) write to register 110 with 0x1c (read mib counter selected) write to register 111 with 0x2e (trigger the read operation) then read register 117 (counter value 31-24) //if bit 31 = 1, there was a counter overflow //if bit 30 = 0, restart (reread) from this register read register 118 (counter value 23-16) read register 119 (counter value 15-8) read register 120 (counter value 7-0) (3) mib counter read (read port 1 tx drop packets) write to register 110 with 0x1d write to register 111 with 0x00 then read register 119 (counter value 15-8) read register 120 (counter value 7-0) note: to read out all the counters, the best performance over the spi bus is (160+3) 8 200 = 260ms, where there are 160 registers , 3 overhead, 8 clocks per access, at 5mhz. in the heaviest condition, the byte counter will overflow in 2 minutes. it is recommended that the software read all the counters at least every 30 seconds. the per port mib counters are designed as ?read cl ear.? a per port mib counter will be clea red after it is accessed. all port dropped packet mib counters are not cleared afte r they are accessed. the application needs to keep track of overflow and valid conditions on these counters.
micrel, inc. ks8995ma/fq semptember 2008 65 m9999-091508 miim registers all the registers defined in this section can be also accessed via the spi interface. note: different mapping mechanisms used for miim and spi. the ?phyad? defined in ie ee is assigned as ?0x1? for port 1, ?0x2? for port 2, ?0x3? for port 3, ?0x4? for port 4, and ?0x5? for port 5. the ?regad? supp orted are 0,1,2,3,4,5. address name description mode default register 0: mii control 15 soft reset 1, phy soft reset. 0, normal operation. r/w 0 14 loop back 1, loop back mode (loopback at mac). 0, normal operation. w 0 13 force 100 1, 100mbps. 0, 10mbps. r/w 1 12 an enable 1, auto-negotiation enabled. 0, auto-negotiation disabled. r/w 1 11 power down 1, power down. 0, normal operation. r/w 0 10 phy isolate 1, electrical ph y isolation of phy from tx+/tx-. 0, normal operation. r/w 0 9 restart an 1, restart auto-negotiation. 0, normal operation. r/w 0 8 force full duplex 1, full duplex. 0, half duplex. r/w 0 7 collision test not supported. ro 0 6 reserved ro 0 5 reserved ro 0 4 force mdi 1, force mdi. 0, normal operation. r/w 0 3 disable auto mdi/mdi-x 1, disable auto mdi/mdi-x. 0, normal operation. r/w 0 2 disable far end fault 1, disable far end fault detection. 0, normal operation. r/w 0 1 disable transmit 1, disable transmit. 0, normal operation. r/w 0 0 disable led 1, disable led. 0, normal operation. r/w 0 register 1: mii status 15 t4 capable 0, not 100 baset4 capable. ro 0 14 100 full capable 1, 100base-tx full-duplex capable. 0, not capable of 100base-tx full-duplex. ro 1 13 100 half capable 1, 100base-tx half-duplex capable. 0, not 100base-tx half-duplex capable. ro 1 12 10 full capable 1, 10 base-t full-duplex capable. 0, not 10base-t full-duplex capable. ro 1 11 10 half capable 1, 10base-t half-duplex capable. 0, 10base-t half-duplex capable. ro 1 10-7 reserved ro 0 6 preamble suppressed not supported. ro 0 5 an complete 1, au to-negotiation complete. 0, auto-negotiation not completed. ro 0 4 far end fault 1, far end fault detected. 0, no far end fault detected. ro 0
micrel, inc. ks8995ma/fq semptember 2008 66 m9999-091508 address name description mode default 3 an capable 1, auto-negotiation capable. 0, not auto-negotiation capable. ro 1 2 link status 1, link is up. 0, link is down. ro 0 1 jabber test not supported. ro 0 0 extended capable 0, not extended register capable. ro 0 register 2: phyid high 15-0 phyid high high order phyid bits. ro 0x0022 register 3: phyid low 15-0 phyid low low order phyid bits. ro 0x1450 register 4: advertisement ability 15 next page not supported. ro 0 14 reserved ro 0 13 remote fault not supported. ro 0 12-11 reserved ro 0 10 pause 1, advertise pause ability. 0, do not advertise pause ability. r/w 1 9 reserved r/w 0 8 adv 100 full 1, advertise 100 full-duplex ability. 0, do not advertise 100 full-duplex ability. r/w 1 7 adv 100 half 1, advertise 100 half-duplex ability. 0, do not advertise 100 half-duplex ability. r/w 1 6 adv 10 full 1, advertise 10 full-duplex ability. 0, do not advertise 10 full-duplex ability. r/w 1 5 adv 10 half 1, advertise 10 half-duplex ability. 0, do not advertise 10 half-duplex ability. r/w 1 4-0 selector field 802.3 ro 00001 register 5: link partner ability 15 next page not supported. ro 0 14 lp ack not supported. ro 0 13 remote fault not supported. ro 0 12-11 reserved ro 0 10 pause link partner pause capability. ro 0 9 reserved ro 0 8 adv 100 full link partner 100 full capability. ro 0 7 adv 100 half link partner 100 half capability. ro 0 6 adv 10 full link partner 10 full capability. ro 0 5 adv 10 half link partner 10 half capability. ro 0 4-0 reserved ro 00001
micrel, inc. ks8995ma/fq semptember 2008 67 m9999-091508 absolute maximum ratings (1) supply voltage (v ddar , v ddap , v ddc ) .......................?0.5v to +2.4v (v ddat , v ddio ) .................................?0.5v to +4.0v input volt age ........................................?0.5v to +4.0v output voltage .....................................?0.5v to +4.0v lead temperature (solder ing, 10 sec.) ..............270c storage temperature (t s ) ................ ?55c to +150c operating ratings (2) supply voltage (v ddar , v ddap , v ddc )....................... +1.7v to +1.9v (v ddat ) ..........+3.15v to +3.45v or +2.4v to +2.6v (v ddio ) ........................................ +3.15v to +3.45v ambient temperature (t a ) commercial .................................... ?0c to +70c industrial ....................................... ?40c to +85c package thermal resistance (3) pqfp ( ja ) no air fl ow........................42.91c/w pqfp ( jc ) no air fl ow ..........................19.6c/w electrical characteristics (4, 5) symbol parameter condition min typ max units 100base-tx operation?all ports 100% utilization i dx 100base-tx (transmitter) v ddat 20 28 ma i ddc 100base-tx (digital co re/pll+ analog rx) v ddc , v ddap , v ddar 157 230 ma i ddio 100base-tx (digital io) v ddio 17 30 ma 10base-t operation ?all ports 100% utilization i dx 10base-t (transmitter) v ddat 15 25 ma i ddc 10base-t (digital core + analog rx) v ddc , v ddap 102 180 ma i ddio 10base-t (digital io) v ddio 6 15 ma auto-negotiation mode i dx 10base-t (transmitter) v ddat 25 40 ma i ddc 10base-t (digital core + analog rx) v ddc , v ddap 108 180 ma i ddio 10base-t (digital io) v ddio 17 20 ma ttl inputs v ih input high voltage +2.0 v v il input low voltage +0.8 v i in input current (excluding pull-up/pull-down) v in = gnd ~ v ddio ?10 10 a ttl outputs v oh output high voltage i oh = ?8ma +2.4 v v ol output low voltage i ol = 8ma +0.4 v i oz output tri-state leakage v in = gnd ~ v ddio 10 a 100base-tx transmit (measured differentially after 1:1 transformer) v o peak differential output voltage 100 ? termination on the differential output 0.95 1.05 v v imb output voltage imbalance 100 ? termination on the differential output 2 % rise/fall time 3 5 ns t r t t rise/fall time imbalance 0 0.5 ns duty cycle distortion 0.5 ns overshoot 5 % v set reference voltage of i set 0.5 v output jitters peak-to-peak 0.7 1.4 ns
micrel, inc. ks8995ma/fq semptember 2008 68 m9999-091508 symbol parameter condition min typ max units 10base-t receive v sq squelch threshold 5mhz square wave 400 mv 10base-t transmit (measured differentially after 1:1 transformer) v ddat = 2.5v v p peak differential output voltage 100 ? termination on the differential output 2.3 v jitters added 100 ? termination on the differential output 16 ns rise/fall times 28 30 ns notes: 1. exceeding the absolute maximu m rating may damage the device. 2. the device is not guaranteed to functi on outside its operating rating. unused inputs must always be tied to an appropriate l ogic voltage level (ground to v dd ). 3. no heat spreader in package. the thermal junction to ambient ( ja ) and the thermal junction to case ( jc ) are under air velocity 0m/s. 4. specification for packaged product only. a single port?s transformer consumes an additional about 40ma for 100base-tx and 59 ma for 10bese- t. 5. measurements were taken with operating ratings.
micrel, inc. ks8995ma/fq semptember 2008 69 m9999-091508 timing diagrams scl sda tcyc1 ts1 th1 receive timing figure 13. eeprom interface input receive timing diagram scl sda tcyc1 transmit timing tov1 figure 14. eeprom interface output transmit timing diagram symbol parameter min typ max units t cyc1 clock cycle 16384 ns t s1 set-up time 20 ns t h1 hold time 20 ns t ov1 output valid 4096 4112 4128 ns table 14. eeprom timing parameters
micrel, inc. ks8995ma/fq semptember 2008 70 m9999-091508 tcyc2 ts2 th2 mtxc mtxen mtxd[0] receive timing figure 15. sni input timing mrxc mrxdv tcyc2 transmit timing tov2 mrxd[0] mcol figure 16. sni output timing symbol parameter min typ max units t cyc2 clock cycle 100 ns t s2 set-up time 10 ns t h2 hold time 0 ns t o2 output valid 0 3 6 ns table 15. sni timing parameters
micrel, inc. ks8995ma/fq semptember 2008 71 m9999-091508 figure 17. mii received timing ? for 100base-t symbol parameter min typ max units t p rxc period 40 ns t wl rxc pulse width 20 ns t wh rxc pulse width 20 ns t su rxd [3:0], rxdv set-up to rising edge of rxc 20 ns t hd rxd [3:0], rxdv hold from rising edge of rxc 20 ns t rlat crs to rxd latency, 4b or 5b aligned 60 ns t od rxd [3:0], rxdv output delay from rising edge of rcx 18 25 28 ns table 16. mii received timing parameters
micrel, inc. ks8995ma/fq semptember 2008 72 m9999-091508 figure 18. mii transmitted timing ? for 100base-t symbol parameter min typ max units t su1 txd [3:0] set-up to txc high 10 ns t su2 txen set-up to txc high 10 ns t hd1 txd [3:0] hold after txc high 0 ns t hd2 txer hold after txc high 0 ns t crs1 txen high to crs asserted latency 40 ns t crs2 txen low to crs de-asserted latency 40 ns table 17. mii transmitted timing parameters
micrel, inc. ks8995ma/fq semptember 2008 73 m9999-091508 spiq spic spid spis_n high impedance msb tchsl tslch tdvch tchdx tdldh tdhdl lsb tclch tchcl tshch tchsh tshsl figure 19. spi input timing symbol parameter min typ max units f c clock frequency 5 mhz t chsl spis_n inactive hold time 90 ns t slch spis_n active set-up time 90 ns t chsh spis_n active hold time 90 ns t shch spis_n inactive set-up time 90 ns t shsl spis_n deselect time 100 ns t dvch data input set-up time 20 ns t chdx data input hold time 30 ns t clch clock rise time 1 s t chcl clock fall time 1 s t dldh data input rise time 1 s t dhdl data input fall time 1 s table 18. spi input timing parameters
micrel, inc. ks8995ma/fq semptember 2008 74 m9999-091508 spid spic spiq spis_n tqlqh tqhql lsb tch tcl tshqz tclqv tclqx figure 20. spi output timing symbol parameter min typ max units f c clock frequency 5 mhz t clqx spiq hold time 0 0 ns t clqv clock low to spiq valid 60 ns t ch clock high time 90 ns t cl clock low time 90 ns t qlqh spiq rise time 50 ns t qhql spiq fall time 50 ns t shqz spiq disable time 100 ns table 19. spi output timing parameters
micrel, inc. ks8995ma/fq semptember 2008 75 m9999-091508 tsr tcs tch trc supply voltage rst_n strap-in value strap-in / output pin figure 21. reset timing symbol parameter min typ max units t sr stable supply voltages to reset high 10 ms t cs configuration set-up time 50 ns t ch configuration hold time 50 ns t rc reset to strap-in pin output 50 ns table 20. reset timing parameters
micrel, inc. ks8995ma/fq semptember 2008 76 m9999-091508 reset circuit diagram micrel recommends the following discrete reset circuit as shown in figure 22 when powering up the ks8895ma device. for the application where the reset circuit signal comes from another device (e.g., cpu, fpga, etc), we recommend the reset circuit as shown in figure 23. vcc r 10k c 10f d1 ks8995ma rst d1: 1n4148 figure 22. recommended reset circuit vcc r 10k d2 c 10f d1 cpu/fpga rst_out_n ks8995ma rst d1, d2: 1n4148 figure 23. recommended circuit for interfacing with cpu/fpga reset at power-on-reset, r, c, and d1 provide the necessary ramp ri se time to reset the micrel device. the reset out from cpu/fpga provides warm reset after power up. it is also recommended to power up the vdd core voltage earlier than vddio voltage. at worst case, the both vdd core an d vddio voltages should come up at the same time.
micrel, inc. ks8995ma/fq semptember 2008 77 m9999-091508 selection of isolation transformer (1) one simple 1:1 isolation transformer is needed at the line in terface. an isolation transformer with integrated common- mode choke is recommended for exceeding fcc requirement s. the following table gives recommended transformer characteristics. characteristics name value test condition turns ratio 1 ct : 1 ct open-circuit inductance (min.) 350h 100mv, 100khz, 8ma leakage inductance (max.) 0.4h 1mhz (min.) inter-winding capacitance (max.) 12pf d.c. resistance (max.) 0.9 ? insertion loss (max.) 1.0db 0mhz to 65mhz hipot (min.) 1500vrms note: 1. the ieee 802.3u standard for 100base-tx assumes a transformer lo ss of 0.5db. for the transmit line transformer, insertion lo ss of up to 1.3db can be compensated by increasing the line drive current by means of reducing the iset resistor value. the following transformer vendors provide com patible magnetic parts for micrel?s device: 4-port integrated single port vendor part auto mdix number of ports vendor part auto mdix number of ports pulse h1164 yes 4 pulse h1102 yes 1 bel fuse 558-5999-q9 yes 4 bel fuse s558-5999-u7 yes 1 ycl ph406466 yes 4 ycl pt163020 yes 1 transpower hb826-2 yes 4 transpower hb726 yes 1 delta lf8731 yes 4 delta lf8505 yes 1 lankom sq-h48w yes 4 lankom lf-h41s yes 1 table 21. qualified magnetics vendors
micrel, inc. ks8995ma/fq semptember 2008 78 m9999-091508 package information pin # 128-pin pqfp (pq)
micrel, inc. ks8995ma/fq semptember 2008 79 m9999-091508 micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http:/www.micrel.com the information furnished by micrel in this data sheet is belie ved to be accurate and reliable. however, no responsibility is a ssumed by micrel for its use. micrel reserves the right to change circuitry and specificati ons at any time without notification to the customer. micrel products are not designed or authori zed for use as components in life support app liances, devices or systems where malfu nction of a product can reasonably be expected to result in personal injury. li fe support devices or systems are devices or systems that (a ) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to resul t in a significant injury to the user. a purchaser?s use or sale of micrel produc ts for use in life support applianc es, devices or systems is a pu rchaser?s own risk and purchaser agrees to fully indemnify micrel fo r any damages resulting from such use or sale. ? 2008 micrel, incorporated.

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